r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 206

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Section 6 Bus Controller (BSC)
6.3.11
REFCR specifies DRAM/synchronous DRAM interface refresh control.
Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424
Note:
Rev. 1.00 Sep. 19, 2008 Page 178 of 1270
REJ09B0466-0100
Bit
15
14
13
12
Group.
Bit Name
CMF
CMIE
RCW1
RCW0
*
Refresh Control Register (REFCR)
Only 0 can be written, to clear the flag.
Initial Value
0
0
0
0
R/W
R/(W)*
R/W
R/W
R/W
Compare Match Interrupt Enable
Description
Compare Match Flag
Status flag that indicates a match between the
values of RTCNT and RTCOR.
[Clearing conditions]
•
•
[Setting condition]
When RTCOR = RTCNT
Enables or disables interrupt requests (CMI) by
the CMF flag when the CMF flag is set to 1.
This bit is valid when refresh control is not
performed. When the refresh control is performed,
this bit is always cleared to 0 and cannot be
modified.
0: Interrupt request by CMF flag disabled
1: Interrupt request by CMF flag enabled
CAS-RAS Wait Control
These bits select the number of wait cycles to be
inserted between the CAS assert cycle and RAS
assert cycle in a DRAM/synchronous DRAM
refresh cycle.
00: Wait state not inserted
01: 1 wait state inserted
10: 2 wait states inserted
11: 3 wait states inserted
When 0 is written to CMF after reading CMF =
1 while the RFSHE bit is cleared to 0
When CBR refreshing is executed while the
RFSHE bit is set to 1