r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 311
r4f2426
Manufacturer Part Number
r4f2426
Description
16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R4F2426.pdf
(1302 pages)
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In a continuous synchronous DRAM space access following a normal space access, the settings of
bits ICIS2, ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads
in different areas, for example, if the second read is a full access to continuous synchronous
DRAM space, only Tp cycle is inserted, and Ti cycle is not. The timing in this case is shown in
figure 6.84.
Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424
Idle Cycle in Case of Continuous Synchronous DRAM Space Access after Normal
Space Access
Figure 6.84 Example of Synchronous DRAM Full Access after External Read
Group.
DQMU, DQML
Precharge-sel
Address bus
Data bus
CKE
CAS
RAS
WE
RD
φ
External space read
T
1
NOP
T
(CAS Latency 2)
2
T
3
PALL ACTV
address
Column
T
Synchronous DRAM space read
p
address
address
Row
Row
T
r
Rev. 1.00 Sep. 19, 2008 Page 283 of 1270
READ
T
c1
Column address
Section 6 Bus Controller (BSC)
T
cl
NOP
T
c2
REJ09B0466-0100
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