r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 954

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Section 16 I
16.3.1
ICCRA is an 8-bit readable/writable register that enables or disables the I
transmission or reception, and selects master or slave mode, transmission or reception, and
transfer clock frequency in master mode.
Rev. 1.00 Sep. 19, 2008 Page 926 of 1270
REJ09B0466-0100
Bit
7
6
5
4
3
2
1
0
Bit Name
ICE
RCVD
MST
TRS
CKS3
CKS2
CKS1
CKS0
I
2
2
C Bus Control Register A (ICCRA)
C Bus Interface 2 (IIC2)
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
I
0: This module is halted.
1: This bit is enabled for transfer operations. (SCL
Reception Disable
This bit enables or disables the next operation
when TRS is 0 and ICDRR is read.
0: Enables next reception
1: Disables next reception
Master/Slave Select
Transmit/Receive Select
When arbitration is lost in master mode, MST and
TRS are both reset by hardware, causing a
transition to slave receive mode. Modification of
the TRS bit should be made between transfer
frames. In addition, TRS is set to 1 automatically
in slave receive mode if the seventh bit of the start
condition matches the slave address set in SAR
and the eighth bit is set to 1.
Operating modes are described below according
to MST and TRS combination.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Transfer Clock Select 3 to 0
In the master mode, these bits should be set
according to the necessary transfer rate (see table
16.2). In the slave mode, they are used to secure
the data setup time in transmit mode. The data
setup time is 10 tcyc if CKS3 is cleared to 0 and
20 tcyc if CKS3 is set to 1.
2
C Bus Interface Enable
and SDA pins are bus drive state.)
2
C bus interface, controls