r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 917
r4f2426
Manufacturer Part Number
r4f2426
Description
16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R4F2426.pdf
(1302 pages)
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1. The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock
4. The SCI checks the TDRE flag at the timing for sending the MSB.
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin maintains the
Figure 15.17 shows a sample flowchart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1.
Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the
RE bit to 0 does not clear the receive error flags.
Serial clock
Serial data
TDRE
TEND
TDR, and transfers the data from TDR to TSR.
transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated.
Because the TXI interrupt routine writes the next transmit data to TDR before transmission of
the current transmit data has finished, continuous transmission can be enabled.
mode has been specified and synchronized with the input clock when use of an external clock
has been specified.
of the next frame is started.
output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request
is generated. The SCK pin is fixed high.
TXI interrupt
request generated
Figure 15.16 Sample SCI Transmission Operation in Clocked Synchronous Mode
Data written to TDR
and TDRE flag
cleared to 0 in TXI
interrupt handling routine
Bit 0
Transfer direction
Bit 1
1 frame
TXI interrupt
request generated
Bit 7
Section 15 Serial Communication Interface (SCI, IrDA)
Bit 0
Rev. 1.00 Sep. 19, 2008 Page 889 of 1270
Bit 1
Bit 6
TEI interrupt
request generated
REJ09B0466-0100
Bit 7
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