r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 1107

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r4f2426

Manufacturer Part Number
r4f2426
Description
16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet

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Section 21 Flash Memory
(5)
Received Data Check
The methods for checking of received data are listed below.
1. Input frequency
The received value of the input frequency is checked to ensure that it is within the range of
minimum to maximum frequencies which matches the clock modes of the specified device. When
the value is out of this range, an input-frequency error is generated.
2. Multiplication ratio
The received value of the multiplication ratio or division ratio is checked to ensure that it matches
a multiplication or division ratio for the clock modes of the specified device. When the value is
out of this range, an input-frequency error is generated.
3. Operating frequency error
The operating frequency is calculated from the received value of the input frequency and the
multiplication or division ratio. The input frequency is input to the LSI and the LSI is operated at
the operating frequency. The expression is given below.
Operating frequency = Input frequency × Multiplication ratio, or
Operating frequency = Input frequency ÷ Division ratio
The calculated operating frequency should be checked to ensure that it is within the range of
minimum to maximum frequencies which are available with the clock modes of the specified
device. When it is out of this range, an operating frequency error is generated.
4. Bit rate
To facilitate error checking, the value (n) of clock select (CKS) in the serial mode register (SMR),
and the value (N) in the bit rate register (BRR), which are found from the peripheral operating
clock frequency (φ) and bit rate (B), are used to calculate the error rate to ensure that it is less than
4%. If the error is 4% or more, a bit rate error is generated. The error is calculated using the
following expression:
φ × 10
6
] − 1} × 100
Error (%) = {[
(2×n − 1)
(N + 1) × B × 64 × 2
Rev. 1.00 Sep. 19, 2008 Page 1079 of 1270
REJ09B0466-0100

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