r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 468

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Section 8 EXDMA Controller (EXDMAC)
8.4.11
(1)
When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three
cycles later. There is a one-cycle bus release interval between the end of a one-transfer-unit
EXDMA cycle and the start of the next transfer.
If there is a transfer request for another channel of higher priority, the transfer request by the
original channel is held pending, and transfer is performed on the higher-priority channel from the
next transfer. Transfer on the original channel is resumed on completion of the higher-priority
channel transfer.
Figures 8.28 to 8.30 show operation timing examples for various conditions.
Rev. 1.00 Sep. 19, 2008 Page 440 of 1270
REJ09B0466-0100
φ pin
Bus cycle
CPU
operation
ETEND
EDA bit
Auto Request/Cycle Steal Mode/Normal Transfer Mode
Examples of Operation Timing in Each Mode
Figure 8.28 Auto Request/Cycle Steal Mode/Normal Transfer Mode
EDA = 1
write
0
Bus release
1
Internal bus space
3 cycles
cycles
(No Contention/Dual Address Mode)
EXDMA
read
EXDMA
write
1 cycle
Bus
release
EXDMA
read
EXDMA
write
Bus
release
EXDMA
Last transfer cycle
read
EXDMA
write
0