r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 434

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Section 8 EXDMA Controller (EXDMAC)
Rev. 1.00 Sep. 19, 2008 Page 406 of 1270
REJ09B0466-0100
Bit
7
6
5
Bit Name
DAT1
DAT0
DARIE
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Destination Address Repeat Interrupt Enable
Description
Destination Address Update Mode
These bits specify incrementing/decrementing of
the transfer destination address (EDDAR). When
an external device with DACK is designated as the
transfer destination in single address mode, the
specification by these bits is ignored.
0×: Fixed
10: Incremented (+1 in byte transfer, +2 in word
11: Decremented (–1 in byte transfer, –2 in word
When this bit is set to 1, in the event of destination
address repeat area overflow the IRF bit is set to 1
and the EDA bit cleared to 0 in EDMDR, and
transfer is terminated. If the EDIE bit in EDMDR is
1 when the IRF bit in EDMDR is set to 1, an
interrupt request is sent to the CPU. When used
together with block transfer mode, a destination
address repeat interrupt is requested at the end of
a block-size transfer. If the EDA bit is set to 1 in
EDMDR for the channel on which transfer is
terminated by a destination address repeat
interrupt, transfer can be resumed from the state
in which it ended. If a destination address repeat
area has not been designated, this bit is ignored.
0: Destination address repeat interrupt is not
1: When destination address repeat area overflow
requested
occurs, the IRF bit in EDMDR is set to 1 and an
interrupt is requested
transfer)
transfer)