r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 417

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

• If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC
(2)
When the MSTP13 bit in MSTPCRH is set to 1, the DMAC clock stops, and the module stop state
is entered. However, 1 cannot be written to the MSTP13 bit if any of the DMAC channels is
enabled. This setting should therefore be made when DMAC operation is stopped.
When the DMAC clock stops, DMAC register accesses can no longer be made. Since the
following DMAC register settings are valid even in the module stop state, they should be
invalidated, if necessary, before a module stop.
• Transfer end/break interrupt (DTE = 0 and DTIE = 1)
• TEND pin enable (TEE = 1)
• DACK pin enable (FAE = 0 and SAE = 1)
register is read as shown in figure 7.40.
Module Stop
φ
DMA internal
address
DMA register
operation
DMA control
Figure 7.40 Contention between DMAC Register Update and CPU Read
Note: The lower word of MAR is the updated value after the operation in [1].
MAR upper
word read
Idle
CPU longword read
MAR lower
word read
[1]
Transfe
source
Read
[2]
DMA read
Rev. 1.00 Sep. 19, 2008 Page 389 of 1270
destination
DMA transfer cycle
Transfer
Write
Section 7 DMA Controller (DMAC)
DMA write
Idle
REJ09B0466-0100