mc68hc908ld64 Freescale Semiconductor, Inc, mc68hc908ld64 Datasheet - Page 76

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mc68hc908ld64

Manufacturer Part Number
mc68hc908ld64
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Configuration Register (CONFIG)
5.4 Configuration Register
Data Sheet
76
NOTE:
Address:
Reset:
SSREC — Short Stop Recovery Bit
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.
COPRS — COP Rate Select Bit
STOP — STOP Instruction Enable Bit
COPD — COP Disable Bit
Read:
Write:
SSREC enables the CPU to exit stop mode with a delay of 32
OSCXCLK cycles instead of a 4096 OSCXCLK cycle delay.
COPRS selects the COP timeout period. Reset clears COPRS. (See
Section 22. Computer Operating Properly
STOP enables the STOP instruction.
COPD disables the COP module. (See
Operating Properly
1 = Stop mode recovery after 32 OSCXCLK cycles
0 = Stop mode recovery after 4096 OSCXCLK cycles
1 = COP timeout period = 2
0 = COP timeout period = 2
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
1 = COP module disabled
0 = COP module enabled
$001F
Bit 7
0
0
Configuration Register (CONFIG)
Figure 5-1. Configuration Register (CONFIG)
= Unimplemented
6
0
0
(COP).)
5
0
0
13
18
4
0
0
– 2
– 2
4
4
SSREC
OSCXCLK cycles
OSCXCLK cycles
3
0
Section 22. Computer
MC68HC908LD64
COPRS
(COP).)
Freescale Semiconductor
2
0
STOP
1
0
Rev. 3.0
COPD
Bit 0
0

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