mc68hc908ld64 Freescale Semiconductor, Inc, mc68hc908ld64 Datasheet - Page 167

• Manufacturer Part Number: mc68hc908ld64
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

MC68HC908LD64
Freescale Semiconductor
NOTE:
NOTE:
—
Rev. 3.0
Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIM status and control register
(TSC).
ELSxB and ELSxA — Edge/Level Select Bits
Before enabling a TIM channel register for input capture operation, make
sure that the TCHx pin is stable for at least two bus clocks.
Notes:
MSxB
1. For CLAMP/TCH0 pin only.
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELS0B and ELS0A are both clear, channel 0 is not connected
to the CLAMP/TCH0 pin. The pin is available as the CLAMP output of
the sync processor.
Table 11-3
ELSxB and ELSxA bits.
X
X
0
0
0
0
0
0
1
1
1
MSxA
0
1
0
0
0
1
1
1
X
X
X
Timer Interface Module (TIM)
Table 11-3. Mode, Edge, and Level Selection
shows how ELSxB and ELSxA work. Reset clears the
ELSxB
0
0
0
1
1
0
1
1
0
1
1
ELSxA
0
0
1
0
1
1
0
1
1
0
1
Compare or
Compare
Capture
or PWM
Buffered
Buffered
Output
Output
Mode
Preset
Output
Input
PWM
Pin is CLAMP of sync processor
Initial Output Level High
Pin is CLAMP of sync processor
Initial Output Level Low
Capture on Rising Edge Only
Capture on Falling Edge Only
Capture on Rising or Falling Edge
Toggle Output on Compare
Clear Output on Compare
Set Output on Compare
Toggle Output on Compare
Clear Output on Compare
Set Output on Compare
Timer Interface Module (TIM)
Configuration
I/O Registers
Data Sheet
(1)
(1)
167
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