mc68hc908ld64 Freescale Semiconductor, Inc, mc68hc908ld64 Datasheet - Page 121

• Manufacturer Part Number: mc68hc908ld64
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

9.4.2.2 Computer Operating Properly (COP) Reset
9.4.2.3 Low-Voltage Inhibit Reset
9.4.2.4 Illegal Opcode Reset
MC68HC908LD64
Freescale Semiconductor
—
Rev. 3.0
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
SIM reset status register (SRSR). The SIM actively pulls down the RST
pin for all internal reset sources.
To prevent a COP module timeout, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and bits 12 through 5
of the SIM counter. The SIM counter output, which occurs at least every
2
serviced as soon as possible out of reset to guarantee the maximum
amount of time before the first timeout.
The COP module is disabled if the RST pin or the IRQ is held at V
while the MCU is in monitor mode. The COP module can be disabled
only through combinational logic conditioned with the high voltage signal
on the RST pin or the IRQ pin. This prevents the COP from becoming
disabled as a result of external noise. During a break state, V
RST pin disables the COP module.
The low-voltage inhibit circuit performs an internal reset when the V
voltage falls to the LVI trip voltage V
is held low while the SIM counter counts out 4096 OSCXCLK cycles.
Sixty-four OSCXCLK cycles later, the CPU and memories are released
from reset to allow the reset vector sequence to occur.
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
If the stop enable bit, STOP, in the configure register (CONFIG) is logic
zero, the SIM treats the STOP instruction as an illegal opcode and
causes an illegal opcode reset. The SIM actively pulls down the RST pin
for all internal reset sources.
12
– 2
4
OSCXCLK cycles, drives the COP counter. The COP should be
System Integration Module (SIM)
TRIPF
. The external reset pin (RST)
System Integration Module (SIM)
Reset and System Initialization
TST
Data Sheet
on the
TST
DD
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