mc68hc908ld64 Freescale Semiconductor, Inc, mc68hc908ld64 Datasheet - Page 306

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mc68hc908ld64

Manufacturer Part Number
mc68hc908ld64
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Input/Output (I/O) Ports
19.6 Port D
19.6.1 Port D Data Register
Data Sheet
306
Alternative Function:
Address:
Port D is an 8-bit special-function port that shares two of its pins with the
multi-master IIC (MMIIC) module, two of its pins with the DDC12AB
module, and four of its pins with the sync processor.
The port D data register (PTD) contains a data latch for each of the eight
port D pins.
PTD[7:0] — Port D Data Bits
IICSDA, IICSCL — Multi-master IIC Data and Clock pins
DDCSCL, DDCSDA — DDC12AB Data and Clock pins
Reset:
Read:
Write:
These read/write bits are software-programmable. Data direction of
each port D pin is under the control of the corresponding bit in data
direction register D. Reset has no effect on port D data.
The PTD7/IICSDA and PTD6/IICSCL pins are multi-master IIC data
and clock pins. When the IICDATE and IICSCLE bits in the port D
control register (PDCR) are clear, the PTD7/IICSDA and
PTD6/IICSCL pins are available for general-purpose I/O.
(See
The PTD4/DDCSCL and PTD5/DDCSDA pins are DDC12AB clock
and data pins respectively. When the DDCSCLE and DDCDATE bits
in the port D control register (PDCR) are clear, the PTD4/DDCSCL
and PTD5/DDCSDA pins are available for general-purpose I/O. (See
19.6.3 Port D
IICSDA
$0003
PTD7
19.6.3 Port D
Bit 7
Figure 19-13. Port D Data Register (PTD)
Input/Output (I/O) Ports
IICSCL
PTD6
Options.)
6
Options.)
DDCSDA DDCSCL
PTD5
5
Unaffected by reset
PTD4
4
HOUT
PTD3
3
MC68HC908LD64
VOUT
PTD2
Freescale Semiconductor
2
PTD1
DE
1
Rev. 3.0
DCLK
PTD0
Bit 0

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