mc68hc908ld64 Freescale Semiconductor, Inc, mc68hc908ld64 Datasheet - Page 307

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mc68hc908ld64

Manufacturer Part Number
mc68hc908ld64
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
19.6.2 Data Direction Register D
MC68HC908LD64
Freescale Semiconductor
Rev. 3.0
Address:
HOUT— Sync Processor HOUT Pulse Output Pin
VOUT — Sync Processor VOUT Pulse Output Pin
DE — Sync Processor DE Pulse Output Pin
DCLK — Sync Processor DCLK Pulse Output Pin
Data direction register D (DDRD) determines whether each port D pin is
an input or an output. Writing a logic 1 to a DDRD bit enables the output
buffer for the corresponding port D pin; a logic 0 disables the output
buffer.
Reset:
Read:
Write:
The PTD3/HOUT pin is the sync processor HOUT pulse output pin.
When the HOUTE bit in the port D control register (PDCR) is clear,
the PTD3/HOUT pin is available for general-purpose I/O. (See
Port D
The PTD2/VOUT pin is the sync processor VOUT pulse output pin.
When the VOUTE bit in the port D control register (PDCR) is clear, the
PTD2/VOUT pin is available for general-purpose I/O. (See
Port D
The PTD1/DE pin is the sync processor DE pulse output pin. When
the DEE bit in the port D control register (PDCR) is clear, the
PTD1/DE pin is available for general-purpose I/O. (See
Options.)
The PTD0/DCLK pin is the sync processor DCLK pulse output pin.
When the DCLKE bit in the port D control register (PDCR) is clear, the
PTD0/DCLK pin is available for general-purpose I/O. (See
Port D
DDRD7
$0007
Bit 7
Figure 19-14. Data Direction Register D (DDRD)
0
Options.)
Options.)
Options.)
Input/Output (I/O) Ports
DDRD6
6
0
DDRD5
5
0
DDRD4
4
0
DDRD3
3
0
DDRD2
2
0
Input/Output (I/O) Ports
DDRD1
19.6.3 Port D
1
0
19.6.3
19.6.3
Data Sheet
19.6.3
DDRD0
Bit 0
Port D
0
307

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