mc68hc908ld64 Freescale Semiconductor, Inc, mc68hc908ld64 Datasheet - Page 247

• Manufacturer Part Number: mc68hc908ld64
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

16.6.7 DDC Data Receive Register (DDCDRR)
MC68HC908LD64
Freescale Semiconductor
—
Rev. 3.0
Address:
If the slave does not return an acknowledge bit (RXAK = 1), the master
will generate a "stop" or "repeated start" condition. The data in the
DDCDTR will not be transferred to the output circuit. The transmit buffer
empty flag remains cleared (TXBE = 0).
The sequence of events for slave transmit and master transmit are
illustrated in
When the DDC module is enabled, DEN = 1, data in this read-only
register depends on whether module is in master or slave mode.
In slave mode, the data in DDCDRR is:
In master mode, the data in the DDCDRR is:
Reset:
Read:
Write:
•
•
•
•
•
the module receives an acknowledge bit (RXAK = 0), after
setting master transmit mode (MRW = 0), and the calling address
has been transmitted; or
the previous data in the output circuit has be transmitted and the
receiving slave returns an acknowledge bit, indicated by a
received acknowledge bit (RXAK = 0).
the calling address from the master when the address match flag
is set (MATCH = 1); or
the last data received when MATCH = 0.
the last data received.
Figure 16-8. DDC Data Receive Register (DDCDRR)
$001B
DRD7
Bit 7
0
Figure
= Unimplemented
DDC12AB Interface
DRD6
6
0
16-9.
DRD5
5
0
DRD4
4
0
DRD3
3
0
DRD2
2
0
DDC12AB Interface
DRD1
1
0
DDC Registers
Data Sheet
DRD0
Bit 0
0
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