mc68hc908ld64 Freescale Semiconductor, Inc, mc68hc908ld64 Datasheet - Page 278

• Manufacturer Part Number: mc68hc908ld64
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

On-Screen Display (OSD)
18.7.2 OSD Status Register (OSDSR)
Data Sheet
278
Address:
CLKPH[1:0] — Pixel Clock Phase Adjustment
HALFCLK — Half Frequency of Pixel Clock
OSDIEN — OSD Interrupt Enable
WRDY — OSD Buffer Write Ready
Reset:
Read:
Write:
These two bits adjust the pixel clock phase to the OSD module. Thus
the OSDR, OSDG, and OSDB outputs can be in phase with video
signals. Reset clears all these bits.
This bit is set to divide the incoming pixel clock by two as the OSD
display clock. Reset clears this bit.
This bit enable OSD interrupt when DENDIF in the OSD status
register is set. Reset clear this bit.
This bit is set when the OSD data registers, $0062 and $0063, are
ready to be loaded with new data. The WRDY is cleared after the CPU
writes to the low byte register, $0062. It becomes set again when the
OSD circuitry has transferred the content of data registers to the
display RAM. Reset sets this bit.
1 = OSD module display clock is PCLK divided-by-2
0 = OSD module display clock is PCLK divided-by-1
1 = DENDIF bit set will generate interrupt request to CPU
0 = DENDIF bit set will not generate interrupt request to CPU
1 = OSD data buffers ready for new data
0 = OSD data buffers busy
WRDY
$0061
Bit 7
1
Figure 18-6. OSD Status Register (OSDSR)
On-Screen Display (OSD)
= Unimplemented
6
5
4
3
MC68HC908LD64
Freescale Semiconductor
2
1
—
DENDIF
Rev. 3.0
0
0
0