ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 89

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 25. Motorola Bus Mode Read States
PS027001-0707
STATE S0
STATE S1
STATE S2
STATE S3
STATE S4
STATE S5
The Read cycle starts in state S0. The CPU drives R/W High to identify a Read cycle.
Entering state S1, the CPU drives a valid address on the address bus, ADDR[23:0].
During state S3, no bus signals are altered.
During state S4, the CPU waits for a cycle termination signal DTACK (WAIT), a peripheral
During state S5, no bus signals are altered.
On the rising edge of state S2, the CPU asserts AS and DS.
signal. If the termination signal is not asserted at least one full CPU clock period prior to the
rising clock edge at the end of S4, the CPU inserts WAIT (T
asserted. Each wait state is a full bus mode cycle.
During Write operations, the Motorola bus mode employs 8 states—S0, S1, S2, S3, S4,
S5, S6, and S7 as described in
eZ80 Bus Mode
Signals (Pins)
ADDR[23:0]
DATA[7:0]
INSTRD
MREQ
IORQ
WAIT
WR
RD
Figure 17. Motorola Bus Mode Signal and Pin Mapping
Table
Bus Mode
Controller
25.
WAIT
Motorola Bus
Signal Equvalents
AS
DS
R/W
DTACK
MREQ
IORQ
ADDR[23:0]
DATA[7:0]
) states until DTACK is
Chip Selects and Wait States
Product Specification
eZ80F91 ASSP
81