ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 337

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 216. EMAC Interrupt Status Register
PS027001-0707
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
7
TxFSMERR_STAT
6
MGTDONE_STAT
5
Rx_CF_STAT
4
Rx_PCF_STAT
3
Rx_DONE_STAT
2
Rx_OVR_STAT
Note:
EMAC Interrupt Status Register
When a Receive overrun occurs, all incoming packets are ignored until the
Rx_OVR_STAT status bit is cleared by software. Consequently, software controls when
the receiver is re-enabled after an overrun. Enable the Rx_OVR interrupt to detect overrun
conditions when they occur. Clear this condition when the Rx buffers are freed to avoid
additional overrun errors. See
Status bits are not self-clearing. Each status bit is cleared by writing a 1 into the selected
bit.
Value
1
0
1
0
1
0
1
0
1
0
1
0
R/W
7
0
Description
An internal error occurs in the EMAC Transmit path. The
Transmit path must be reset to reset this error condition.
Normal operation—no Transmit state machine errors.
The MII Management interrupt has completed a Read
(RSTAT or SCAN) or a Write (LDCTLD) access to the
PHY.
The MII Management interrupt does not occur.
Receive Control Frame interrupt (Receive Interrupt)
occurs.
Receive Control Frame interrupt does not occur.
Receive Pause Control Frame interrupt (Receive
Interrupt) occurs.
Disable Receive Pause Control Frame interrupt (Receive
Interrupt) does not occur.
Receive Done interrupt (Receive Interrupt) occurs.
Disable Receive Done interrupt (Receive Interrupt) does
not occur.
Receive Overrun interrupt (System Interrupt) occurs.
Receive Overrun interrupt (System Interrupt) does not
occur.
R/W
6
0
R/W
5
0
Table
(EMAC_ISTAT = 004Dh)
R/W
4
0
216.
R/W
3
0
R/W
2
0
R/W
Ethernet Media Access Controller
1
0
Product Specification
R/W
0
0
eZ80F91 ASSP
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