ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 339

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 218. EMAC PHY Read Status Data Register—High Byte
Table 219. EMAC MII Status Register
PS027001-0707
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
[7:0]
EMAC_PRSD_H
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
7
BUSY
6
MIILF
EMAC MII Status Register
The EMAC MII Status Register is used to determine the current state of the external PHY
device. See
Value
1
0
1
0
Value
00h–FFh These bits represent the High byte of the 2-byte EMAC
Description
MII management operation in progress—Busy. This status bit
goes busy whenever the LCTLD (PHY Write) or the RSTAT
(PHY Read) is set in the EMAC_MIIMGT register. It is
negated when the Write or Read operation to the PHY has
completed. In SCAN mode, the BUSY will be asserted until
the SCAN is disabled. Use the EmacIStat[MGTDONE]
interrupt status bit to determine when the data is valid.
Not Busy.
Local copy of PHY Link fail bit.
PHY Link OK.
R
R
7
0
7
0
Table
Description
PHY Read Status Data value, {EMAC_PRSD_H,
EMAC_PRSD_L}. Bit 7 is bit 15 (msb) of the 16-bit value.
Bit 0 is bit 8 of the 16-bit value.
219.
R
R
6
0
6
0
(EMAC_MIISTAT = 0050h)
R
R
5
0
5
0
R
R
4
0
4
0
R
R
3
0
3
0
R
R
2
0
2
0
(EMAC_PRSD_H = 004Fh)
Ethernet Media Access Controller
R
R
1
0
1
0
Product Specification
R
R
0
0
0
0
eZ80F91 ASSP
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