ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 141

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
Timer Interrupt Enable Register
The Timer x Interrupt Enable Register (see
operations. Only bits related to functions present in a given timer are active.
Table 55. Timer Interrupt Enable
TMR2_IER = 0070h, TMR3_IER = 0075h)
1
RLD
0
TIM_EN
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
7
6
IRQ_OC3_EN
5
IRQ_OC2_EN
4
IRQ_OC1_EN
3
IRQ_OC0_EN
0
1
0
1
Value
0
0
1
0
1
0
1
0
1
Reload function is not forced.
Force reload. When 1 is written to this bit, the values in the
reload registers are loaded into the downcounter.
The programmable reload timer is disabled.
The programmable reload timer is enabled.
R/W
Description
Unused.
Interrupt requests for OC3 are disabled (valid only in
OUTPUT COMPARE mode). OC operations occur in Timer 3.
Interrupt requests for OC3 are enabled (valid only in OUTPUT
COMPARE mode). OC operations occur in Timer 3.
Interrupt requests for OC2 are disabled (valid only in
OUTPUT COMPARE mode). OC operations occur in Timer 3.
Interrupt requests for OC2 are enabled (valid only in OUTPUT
COMPARE mode). OC operations occur in Timer 3.
Interrupt requests for OC1 are disabled (valid only in
OUTPUT COMPARE mode). OC operations occur in Timer 3.
Interrupt requests for OC1 are enabled (valid only in OUTPUT
COMPARE mode). OC operations occur in Timer 3.
Interrupt requests for OC0 are disabled (valid only in
OUTPUT COMPARE mode). OC operations occur in Timer 3.
Interrupt requests for OC0 are enabled (valid only in OUTPUT
COMPARE mode). OC operations occur in Timer 3.
7
0
R/W
6
0
(TMR0_IER = 0061h, TMR1_IER = 0066h,
R/W
Table
5
0
55) is used to control timer interrupt
R/W
4
0
R/W
3
0
Programmable Reload Timers
Product Specification
R/W
2
0
eZ80F91 ASSP
R/W
1
0
R/W
0
0
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