ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 326

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 199. EMAC PHY Configuration Data Register—Low Byte
PS027001-0707
Bit
Position
[2:0]
CLKS
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
EMAC_CTLD_L
EMAC PHY Configuration Data Register—Low and High Byte
The Low and High bytes of the EMAC PHY Configuration Data Register represents the
configuration data written to the external PHY. The EMAC_CTLD_H and
EMAC_CTLD_L registers form a 16-bit register. These registers are loaded with data to
be sent via the MDIO pin to the PHY. The PHY is selected by setting the EMAC_FIAD.
The register inside the PHY is selected by setting EMAC_RGAD. See
Table 200
Value
Programmable divisor that produces MDC from SCLK. MDC is the
management data clock pin, which clocks MDIO data to and from the
PHY. its frequency is SCLK divided by the MDC clock divider.
000
001
010
011
100
101
110
111
Value
00h–
FFh
Description
MDC = SCLK ÷ 4.
MDC = SCLK ÷ 4.
MDC = SCLK ÷ 6.
MDC = SCLK ÷ 8.
MDC = SCLK ÷ 10.
MDC = SCLK ÷ 14.
MDC = SCLK ÷ 20.
MDC = SCLK ÷ 28.
R/W
on page 319.
7
0
Description
These bits represent the Low byte of the 2 byte PHY
configuration data value, {EMAC_CTLD_H,
EMAC_CTLD_L}. Bit 7 is bit 7 of the 16 bit value. Bit 0 is bit
0 (lsb) of the 16 bit value.
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
(EMAC_CTLD_L = 003Ch)
R/W
Ethernet Media Access Controller
1
0
Product Specification
R/W
0
0
Table 199 and
eZ80F91 ASSP
318