ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 207

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

eZ80F91 ASSP
Product Specification
199
period. If the data to be received is a logical 0, a delayed Low (0) pulse is output on RxD.
Data transmission is illustrated in
Figure
39.
16-clock
period
Baud Rate
Clock
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
IR_RxD
UART_RxD
16-clock
16-clock
16-clock
16-clock
8-clock
period
period
period
period
delay
Figure 39. Infrared Data Reception
The IrDA endec is designed to ignore pulses on IR_RxD which do not comply with IrDA
pulse width specifications. Input pulses wider than five baud clocks (that is, 5/16 of a bit
period) are always ignored, as this would be a violation of the maximum pulse width spec-
ified for any standard baud rate up to 115.2 kbps. The check for minimum pulse widths is
optional, since using a slow system clock frequency limits the ability to accurately mea-
sure narrow pulse widths near the IrDA specification minimum of 1.41 us for the
2.4–115.2 kbps rate range.
To enable checks of minimum input pulse width on IR_RxD, a non-zero value must be
programmed into the MIN_PULSE field of IR_CTL (bits [7:4]). This field forms the
most-significant four bits of the 6-bit down-counter used to determine if an input pulse
will be ignored because it is too narrow. The lower two counter bits are hard-coded to load
with 0x3, resulting in a total down-count equal to ((MIN_PULSE* 4) + 3). To be accepted,
input pulses must have a width greater than or equal to the down-count value times the
system clock period.
The following equation is used to determine an appropriate setting for MIN_PULSE:
MIN_PULSE = INT( ((F
*W
) - 3) / 4 )
sys
min
Where
F
is the frequency of the system clock, and,
sys
W
is the minimum width of recognized input pulses.
min
PS027001-0707
Infrared Encoder/Decoder