ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 80

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
Z80 bus mode Read and Write timing is illustrated in
The Z80 bus mode states are configured for 1 to 15 CPU system clock cycles. In the fig-
ures, each Z80 bus mode state is two CPU system clock cycles in duration. The figures
also illustrate the assertion of 1 wait state (T
Z80 bus mode cycle.
System Clock
ADDR[23:0]
DATA[7:0]
or IORQ
MREQ
WAIT
CSx
WR
RD
Figure 10. Example: Z80 Bus Mode Read Timing
T1
T2
WAIT
T
CLK
) by the external peripheral during each
Figure 10
T3
and
Chip Selects and Wait States
Product Specification
Figure 11
eZ80F91 ASSP
on page 73.
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