ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 73

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Chip Selects and Wait States
PS027001-0707
Memory and I/O Chip Selects
Memory Chip Select Operation
The eZ80F91 generates four chip selects for external devices. Each chip select is pro-
grammed to access either the memory space or the I/O space. The memory chip selects are
individually programmed on a 64 KB boundary. Each I/O chip selects choose a 256-byte
section of I/O space. In addition, each chip select is programmed for up to 7 Wait states.
Each of the chip selects are enabled either for the memory address space or the I/O address
space, but not both. To select the memory address space for a particular chip select,
CSX_IO (CSx_CTL[4]) must be reset to 0. To select the I/O address space for a particular
chip select, CSX_IO must be set to 1. After RESET, the default is for all chip selects to be
configured for the memory address space. For either the memory address space or the I/O
address space, the individual chip selects must be enabled by setting CSX_EN
(CSx_CTL[3]) to 1.
Operation of each of the memory chip select is controlled by three control registers. To
enable a particular memory chip select, the following conditions must be satisfied:
•
•
•
•
•
•
•
If all the preceding conditions are satisfied to generate a memory chip select, then the fol-
lowing results occur:
•
•
•
The chip select is enabled by setting CSx_EN to 1.
The chip select is configured for memory by clearing CSX_IO to 0.
The address is in the associated chip select range:
CSx
On-chip Flash is not configured for the same address space, because on-chip Flash is
prioritized higher than all memory chip selects.
On-chip RAM is not configured for the same address space, because on-chip RAM is
prioritized higher than Flash and all memory chip selects.
No higher priority (lower number) chip select meets the above conditions.
A memory access instruction must be executing.
The appropriate chip select—CS0, CS1, CS2, or CS3 is asserted (driven Low).
MREQ is asserted (driven Low).
Depending on the instruction either RD or WR is asserted (driven Low).
_LBR[7:0]
≤
ADDR[23:16]
≤ CSx
_UBR[7:0].
Chip Selects and Wait States
Product Specification
eZ80F91 ASSP
65