ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 236

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
enters MASTER mode when the bus is released. The STA bit is automatically cleared after
a START condition is set. Writing 0 to the STA bit produces no effect.
If the Master Mode Stop bit (STP) is set to 1 in MASTER mode, a STOP condition is
transmitted on the I
ates as if a STOP condition is received, but no STOP condition is transmitted. If both STA
and STP bits are set, the I
mode), then transmits the START condition. The STP bit is cleared to 0 automatically.
Writing a 0 to this bit produces no effect.
The I
I
set to 1 and the IEN bit is also set, an interrupt is generated. When IFLG is set by the I
the Low period of the I
When a 0 is written to IFLG, the interrupt is cleared and the I
When the I
acknowledge clock pulse on the I
•
•
•
When AAK is cleared to 0, a NACK is sent when a data byte is received in MASTER or
SLAVE mode. If AAK is cleared to 0 in SLAVE TRANSMIT mode, the byte in the
I
block enters the
to its slave address unless AAK is set to 1. See
2
2
C states is entered. The only state that does not set the IFLG bit is state
C_DR register is assumed to be the final byte. After this byte is transmitted, the I
Either the whole of a 7-bit slave address or the first or second byte of a 10-bit slave ad-
dress is received.
The general call address is received and the General Call Enable bit in I
to 1.
A data byte is received while in MASTER or SLAVE modes.
2
C Interrupt Flag (IFLG) is set to 1 automatically when any of 30 of the possible 31
2
C Acknowledge bit (AAK) is set to 1, an acknowledge is sent during the
C8h
2
C bus. If the STP bit is set to 1 in SLAVE mode, the I
state, then returns to an idle state. The I
2
C bus clock line is stretched and the data transfer is suspended.
2
C block first transmits the STOP condition (if in MASTER
2
C bus if:
Table 127
on page 229.
2
2
C module does not respond
C clock line is released.
Product Specification
I
2
C Serial I/O Interface
eZ80F91 ASSP
F8h
2
C module oper-
2
C_SAR is set
. If IFLG is
2
C
2
C,
228