ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 361

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 240. External I/O Read Timing
PS027001-0707
Parameter
T
T
T
T
T
T
T
1
2
3
4
5
6
7
External I/O Read Timing
ADDR[23:0]
DATA[7:0]
Abbreviation
PHI Clock Rise to ADDR Valid Delay
PHI Clock Rise to ADDR Hold Time
DATA Valid to PHI Clock Rise Setup Time
PHI Clock Rise to DATA Hold Time
PHI Clock Rise to CSx Assertion Delay
PHI Clock Rise to CSx Deassertion Delay
PHI Clock Rise to IORQ Assertion Delay
(input)
IORQ
CSx
Figure 70
signal transition timing is independent of the particular bus mode employed (eZ80
Intel, or Motorola).
PHI
RD
and
Table 240
T
T
Figure 70. External I/O Read Timing
7
9
T
T
1
5
display the timing for external I/O reads. PHI clock rise/fall to
T
CLK
Minimum
1.0
0.5
0.0
2.0
0.0
2.6
—
T
Delay (ns)
3
T
T
2
T
Maximum
T
6
10
8
6.0
7.3
8.5
7.0
—
—
—
T
4
Product Specification
Electrical Characteristics
eZ80F91 ASSP
®
, Z80,
353