ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 165

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
Pulse-Width Modulation Rising Edge—Low Byte
A parallel 16-bit Write of {TMR3_PWMxR_H[7–0], TMR3_PWMxR_L[7–0]} occurs
when software initiates a Write to TMR3_PWMxR_L. The register is described in
Table
Table 76. PWMx Rising-Edge Register—Low Byte
TMR3_PWM1R_L = 007Eh, TMR3_PWM2R_L = 0080h, TMR3_PWM3R_L = 0082h)
Pulse-Width Modulation Rising Edge—High Byte
Writing to TMR3_PWMxR_H stores the value in a temporary holding register. A parallel
16-bit Write of {TMR3_PWMxR_H[7–0], TMR3_PWMxR_L[7–0]} occurs when soft-
ware initiates a Write to TMR3_PWMxR_L. The register is detailed in
Table 77. PWMx Rising-Edge Register—High Byte
TMR3_PWM1R_H = 007Fh, TMR3_PWM2R_H = 0081h, TMR3_PWM3R_H = 0083h)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
PWMXR_L
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
PWMXR_H
76.
Value
00h–FFh
Value
00h–FFh
Description
These bits represent the Low byte of the 16-bit value to set the
rising edge COMPARE value for PWMx,
{TMR3_PWMXR_H[7:0], TMR3_PWMXR_L[7:0]}. Bit 7 is bit 7
of the 16-bit timer data value. Bit 0 is bit 0 (lsb) of the
16-bit timer data value.
Description
These bits represent the High byte of the 16-bit value to set the
rising edge COMPARE value for PWMx,
{TMR3_PWMXR_H[7:0], TMR3_PWMXR_L[7:0]}. Bit 7 is bit
15 (msb) of the 16-bit timer data value. Bit 0 is bit 8 of the
16-bit timer data value.
R/W
R/W
7
0
7
0
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
R/W
R/W
4
0
4
0
R/W
R/W
(TMR3_PWM0R_L = 007Ch,
(TMR3_PWM0R_H = 007Dh,
3
0
3
0
Programmable Reload Timers
Product Specification
R/W
R/W
2
0
2
0
Table
eZ80F91 ASSP
R/W
R/W
1
0
1
0
77.
R/W
R/W
0
0
0
0
157