ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 131

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
TMR3_CTL Write
Interrupt Request
(Timer Enable)
System Clock
Clock Enable
T3 Count
Minimum time-out duration is four times longer than the input clock period and is gener-
ated by setting the clock divider ratio to 1:4 and the reload value to
time-out duration is 2
erated by setting the clock divider ratio to 1:256 and the reload value to
SINGLE PASS Mode
In SINGLE PASS mode when the end-of-count value (
the timer is disabled, and TMRx_CTL[TIM_EN] bit resets to 0. To re-enable the timer, the
CPU must set the TIM_EN bit to 1. An example of a PRT operating in SINGLE PASS
mode is illustrated in
Table 50. Example: PRT SINGLE PASS Mode Parameters
CONTINUOUS Mode
In CONTINUOUS mode, when the end-of-count value,
automatically reloads the 16-bit start value from the Timer Reload registers,
Parameter
Timer Enable
Reload
Prescaler Divider = 4
SINGLE PASS Mode
End of Count Interrupt Enable
Timer Reload Value
Figure 27. Example: PRT SINGLE PASS Mode Operation
0
24
Figure
(16,777,216) times longer than the input clock period and is gen-
4
27. Timer register information is indicated in
Control Register(s)
TMR
TMR
TMR
TMR
TMR
{TMR
3
x
x
x
x
x
x
_CTL[TIM_EN]
_CTL[RLD]
_CTL[CLK_DIV]
_CTL[TIM_CONT]
_IER[IRQ_EOC_EN]
_RR_H, TMRx_RR_L}
2
0000h
0000h
1
) is reached; counting halts,
Programmable Reload Timers
, is reached, the timer
Product Specification
0001h
Value
1
1
00b
0
1
0004h
0000h
eZ80F91 ASSP
. Maximum
Table
0
.
50.
123