ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 106

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

PS027001-0707
eZ80 Core
Interface
System Clock
Flash Memory Overview
Reading Flash Memory
The eZ80F91 device includes a Flash memory controller that automatically converts
standard CPU Read and Write cycles to the specific protocol required for the Flash
memory array. As such, standard memory Read and Write instructions access the Flash
memory array as if it is internal RAM. The controller also supports I/O access to the Flash
memory array, in effect presenting it as an indirectly addressable bank of I/O registers.
These access methods are also supported via the ZDI and OCI™ interfaces.
In addition, eZ80AcclaimPlus!™ Flash Microcontrollers support a Flash Read–While–
Write methodology. In other words, the eZ80 CPU continues to read and execute code
from an area of Flash memory when a nonconflicting area of Flash memory is being pro-
grammed.
The Flash memory controller contains a frequency divider, a Flash register interface, and a
Flash control state machine. A simplified block diagram of the Flash controller is
illustrated in
The main Flash memory array is read using both memory and I/O operations. As an auxil-
iary storage area, the information page is only accessible via I/O operations. In all cases,
Wait states are automatically inserted to allow for read access time.
ADDR
D
OUT
17
8
Registers
Figure 24. Flash Memory Block Diagram
Figure
8-bit downcounter
Control
Flash
Clock Divider
24.
Machine
Flash
State
FADDR
FD
FCNTL
MAIN_INFO
CPUD
FLASH_IRQ
IN
OUT
17
8
9
8
Product Specification
512 bytes
256 KB
Flash
+
eZ80F91 ASSP
Flash Memory
FD
OUT
8
98