ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 60

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

eZ80F91 ASSP
Product Specification
52
function, PC5 drives the DSR1 signal to UART1. As this signal is Low level true, the
DSR1 signal to UART1 is driven to 1 when PC5 is not in alternate mode function.
GPIO Mode 8—Level Sensitive Interrupt
The port pin is configured for level-sensitive interrupt mode. The value in the Port x Data
register determines if a low or high-level causes an interrupt request. An interrupt request
is generated when the level at the pin is the same as the level stored in the Port x Data
register. The port pin value is sampled by the system clock. The input pin must be held at
the selected interrupt level for a minimum of two system clock periods to initiate an
interrupt. The interrupt request remains active as long as this condition is maintained at the
external source. For example, if a port pin is configured as a low-level-sensitive interrupt,
the interrupt request will be asserted when the pin has been low for two system clocks and
remains active until the pin goes high.
Configuring a pin for mode 8 requires a transition through mode 9 (edge triggered mode).
To avoid the possibility of an unwanted interrupt while transition through mode 9, the
following steps must be taken to select mode 8 when starting from the default mode (mode
2):
1. Disable interrupts
2. Set Px_DR = 0 (low level interrupt) or 1 (high level interrupt)
3. Set Px_ALT2 = 1
4. Set Px_ALT1 =1 (mode 9)
5. Set Px_DDR = 0 (mode 8)
6. Set Px_ALT0 = 1 (to clear possible mode 9 interrupt)
7. Enable interrupts
GPIO Mode 9—Edge Triggered Interrupt
The port pin is configured for single edge triggered interrupt mode. The value in the Port x
Data register determines whether a positive or negative edge causes an interrupt request.
Writing 0 to the Port x Data register bit sets the selected pin to generate an interrupt
request for falling edges. Writing 1 to the Port x Data register bit sets the selected pin to
generate an interrupt request for rising edges. The interrupt request remains active until 1
is written to the corresponding bit of the Port x Alternate register 0. To select mode 9 from
the default mode (mode 2), you must:
1. Set the Port x Data register
2. Set Px_ALT2 = 1
3. Set Px_ALT1 = 1
4. Set Px_DDR=1
PS027001-0707
General Purpose Input/Output