ez80f91 ZiLOG Semiconductor, ez80f91 Datasheet - Page 58

• Manufacturer Part Number: ez80f91
• Description: Ez80 Acclaimplus!? Connectivity Assp Ez80f91 Assp
• Manufacturer: ZiLOG Semiconductor

Table 6. GPIO Mode Selection
PS027001-0707
GPIO
Mode
1
2
3
4
5
6
7
8
9
Px_ALT2
Bits7:0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Figure 5
pin for the various modes.
GPIO Mode 1—Output
The port pin is configured as a standard digital output pin. The value written to the Port x
Data register (Px_DR) is driven on the pin.
GPIO Mode 2—Input
The port pin is configured as a standard digital input pin. The output is high impedance.
The value stored in the Port x Data register produces no effect. As in all modes, a read
from the Port x Data register returns the pin’s value. GPIO mode 2 is the default operating
mode following a RESET.
Px_ALT1
Bits7:0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
and
Px_DDR
Figure 6
Bits7:0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
on page 53 display the simplified block diagrams of the GPIO port
Bits7:0 Port Mode
Px_DR
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output
Output
Input from pin
Input from pin
Open-drain output
Open-drain I/O
Open-source I/O
Open-source output
Reserved
Interrupt—dual edge-triggered
Alternate function controls port I/O.
Alternate function controls port I/O.
Interrupt—active Low
Interrupt—active High
Interrupt—falling edge-triggered
Interrupt—rising edge-triggered
General Purpose Input/Output
Product Specification
0
1
High impedance
High impedance
0
High impedance
High impedance
1
High impedance
High impedance
Output
High impedance
High impedance
High impedance
High impedance
eZ80F91 ASSP
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