XC2V8000-5BF957C Xilinx, Inc., XC2V8000-5BF957C Datasheet - Page 8

• Manufacturer Part Number: XC2V8000-5BF957C
• Description: Virtex-II 1.5V Field-Programmable Gate Array
• Manufacturer: Xilinx, Inc.

DS031-2 (v1.8) October 12, 2001
Detailed Description
Input/Output Blocks (IOBs)
Virtex-II I/O blocks (IOBs) are provided in groups of two or
four on the perimeter of each device. Each IOB can be used
as input and/or output for single-ended I/Os. Two IOBs can
be used as a differential pair. A differential pair is always
connected to the same switch matrix, as shown in
IOB blocks are designed for high performances I/Os, sup-
porting 19 single-ended standards, as well as differential
signaling with LVDS, LDT, Bus LVDS, and LVPECL.
Supported I/O Standards
Virtex-II IOB blocks feature SelectI/O inputs and outputs
that support a wide variety of I/O signaling standards. In
addition to the internal supply voltage (V
put driver supply voltage ( V
standard (see
(V
dard used. For exact supply voltage absolute maximum rat-
ings, see
DS031-2 (v1.8) October 12, 2001
Advance Product Specification
CCAUX
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
Switch
Matrix
= 3.3 V) is required, regardless of the I/O stan-
DC Input and Output
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Figure 1: Virtex-II Input/Output Tile
Table
1). An auxiliary supply voltage
CCO
PAD4
PAD3
PAD2
PAD1
R
IOB
IOB
IOB
IOB
Levels.
) is dependent on the I/O
CCINT
Differential Pair
Differential Pair
DS031_30_101600
= 1.5V), out-
Figure
0
0
www.xilinx.com
1-800-255-7778
1.
0
Virtex-II 1.5V
Field-Programmable Gate Arrays
Advance Product Specification
Table 1: Supported Single-Ended I/O Standards
Notes:
1.
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3
PCI66_3
PCI-X
GTL
GTLP
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
AGP-2X/AGP
Standard
V
termination voltage or the voltage seen at the I/O pad.
CCO
I/O
of GTL or GTLP should not be lower than the
Output
Note 1
Note 1
V
3.3
3.3
2.5
1.8
1.5
3.3
3.3
3.3
1.5
1.5
1.5
1.5
2.5
2.5
3.3
3.3
3.3
CCO
Note 1
Note 1
Input
V
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.3
3.3
2.5
1.8
1.5
3.3
3.3
3.3
CCO
Input
V
0.75
0.75
1.25
1.25
1.32
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.8
1.0
0.9
0.9
1.5
1.5
REF
Voltage (V
Termination
Module 2 of 4
Board
0.75
0.75
1.25
1.25
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.2
1.5
1.5
1.5
1.5
1.5
TT
)
1