XC2V8000-5BF957C Xilinx, Inc., XC2V8000-5BF957C Datasheet - Page 29

• Manufacturer Part Number: XC2V8000-5BF957C
• Description: Virtex-II 1.5V Field-Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Virtex-II 1.5V Field-Programmable Gate Arrays
Single-Port Configuration
As a single-port RAM, the block SelectRAM has access to
the 18-Kbit memory locations in any of the 2K x 9-bit,
1K x 18-bit, or 512 x 36-bit configurations and to 16-Kbit
memory locations in any of the 16K x 1-bit, 8K x 2-bit, or
4K x 4-bit configurations. The advantage of the 9-bit, 18-bit
and 36-bit widths is the ability to store a parity bit for each
eight bits. Parity bits must be generated or checked exter-
nally in user logic. In such cases, the width is viewed as 8 +
1, 16 + 2, or 32 + 4. These extra parity bits are stored and
behave exactly as the other bits, including the timing param-
eters. Video applications can use the 9-bit ratio of Virtex-II
block SelectRAM memory to advantage.
Each block SelectRAM cell is a fully synchronous memory
as illustrated in
bus widths are identical.
Table 15: Dual-Port Mode Configurations
If both ports are configured in either 2K x 9-bit, 1K x 18-bit,
or 512 x 36-bit configurations, the 18-Kbit block is accessi-
ble from port A or B. If both ports are configured in either
16K x 1-bit, 8K x 2-bit. or 4K x 4-bit configurations, the
Module 2 of 4
22
Port A
Port B
Port A
Port B
Port A
Port B
Port A
Port B
Port A
Port B
Port A
Port B
Figure 28: 18-Kbit Block SelectRAM Memory in
Figure
DI
DIP
ADDR
WE
EN
SSR
CLK
18-Kbit Block SelectRAM
512 x 36
512 x 36
16K x 1
16K x 1
1K x 18
1K x 18
Single-Port Mode
8K x 2
8K x 2
4K x 4
4K x 4
2K x 9
2K x 9
28. Input data bus and output data
512 x 36
DOP
16K x 1
1K x 18
1K x 18
8K x 2
4K x 4
2K x 9
2K x 9
8K x 2
4K x 4
DO
DS031_10_102000
www.xilinx.com
1-800-255-7778
512 x 36
16K x 1
1K x 18
4K x 4
8K x 2
2K x 9
4K x 4
2K x 9
Dual-Port Configuration
As a dual-port RAM, each port of block SelectRAM has
access to a common 18-Kbit memory resource. These are
fully synchronous ports with independent control signals for
each port. The data widths of the two ports can be config-
ured independently, providing built-in bus-width conversion.
Table 15
ports A & B.
16 K-bit block is accessible from Port A or Port B. All other
configurations result in one port having access to an 18-Kbit
memory block and the other port having access to a 16 K-bit
subset of the memory block equal to 16 Kbits.
illustrates the different configurations available on
512 x 36
16K x 1
1K x 18
2K x 9
8K x 2
4K x 4
512 x 36
16K x 1
1K x 18
DS031-2 (v1.8) October 12, 2001
8K x 2
Advance Product Specification
512 x 36
16K x 1
R