XC2V8000-5BF957C Xilinx, Inc., XC2V8000-5BF957C Datasheet - Page 69

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XC2V8000-5BF957C

Manufacturer Part Number
XC2V8000-5BF957C
Description
Virtex-II 1.5V Field-Programmable Gate Array
Manufacturer
Xilinx, Inc.
Datasheet
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, Without DCM
Table 29: Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, Without DCM
DS031-3 (v1.9) October 12, 2001
Advance Product Specification
Notes:
1.
2.
LVTTL Global Clock Input to Output Delay using
Output Flip-flop, 12 mA, Fast Slew Rate, without
DCM.
For data output with different standards, adjust
the delays with the values shown in
Switching Characteristics Standard
Adjustments, page
Global Clock and OFF without DCM
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured at 50% V
Table
18.
R
Description
13.
CC
IOB Output
threshold with 35 pF external capacitive load. For other I/O standards and different loads, see
www.xilinx.com
1-800-255-7778
Symbol
T
ICKOF
Device
2v1000
2v1500
2v2000
2v3000
2v4000
2v6000
2v8000
2v250
2v500
2v40
2v80
Virtex-II 1.5V Field-Programmable Gate Arrays
TBD
4.3
4.3
4.5
4.5
5.1
5.1
5.2
5.2
5.5
5.8
6
Speed Grade
4.7
4.7
5.0
5.0
5.4
5.4
5.6
5.7
6.0
6.3
6.3
5
5.0
5.0
5.8
5.8
5.9
5.9
6.1
6.6
6.9
7.3
7.3
4
Module 3 of 4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
23

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