XC2V8000-5BF957C Xilinx, Inc., XC2V8000-5BF957C Datasheet - Page 30

• Manufacturer Part Number: XC2V8000-5BF957C
• Description: Virtex-II 1.5V Field-Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Each block SelectRAM cell is a fully synchronous memory,
as illustrated in
inputs and outputs and are independently clocked.
Port Aspect Ratios
Table 16
18-Kbit block SelectRAM. Virtex-II block SelectRAM also
includes dedicated routing resources to provide an efficient
interface with CLBs, block SelectRAM, and multipliers.
DS031-2 (v1.8) October 12, 2001
Advance Product Specification
Figure 29: 18-Kbit Block SelectRAM in Dual-Port Mode
shows the depth and the width aspect ratios for the
R
Figure
DIPA
ADDRA
WEA
ENA
SSRA
DIB
DIPB
ADDRB
WEB
ENB
SSRB
DIA
CLKA
CLKB
18-Kbit Block SelectRAM
29. The two ports have independent
RAM Contents
Data_out
Address
Data_in
Data_in
CLK
WE
DOPA
DOPB
DOA
DOB
DS031_11_102000
Figure 30: WRITE_FIRST Mode
DI
New
Old
aa
Internal
Memory
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Table 16: 18-Kbit Block SelectRAM Port Aspect Ratio
Read/Write Operations
The Virtex-II block SelectRAM read operation is fully syn-
chronous. An address is presented, and the read operation
is enabled by control signals WEA and WEB in addition to
ENA or ENB. Then, depending on clock polarity, a rising or
falling clock edge causes the stored data to be loaded into
output registers.
The write operation is also fully synchronous. Data and
address are presented, and the write operation is enabled
by control signals WEA or WEB in addition to ENA or ENB.
Then, again depending on the clock input mode, a rising or
falling clock edge causes the data to be loaded into the
memory cell addressed.
A write operation performs a simultaneous read operation.
Three different options are available, selected by configura-
tion:
1. “WRITE_FIRST”
DO
Width
18
36
1
2
4
9
The “WRITE_FIRST” option is a transparent mode. The
same clock edge that writes the data input (DI) into the
memory also transfers DI into the output registers DO
as shown in
Virtex-II 1.5V Field-Programmable Gate Arrays
16,384
Depth
8,192
4,096
2,048
1,024
Data_out = Data_in
512
New
New
Figure
Address Bus
ADDR[13:0]
ADDR[12:0]
ADDR[11:0]
ADDR[10:0]
DS031_14_102000
ADDR[9:0]
ADDR[8:0]
30.
DATA[15:0]
DATA[31:0]
Data Bus
DATA[1:0]
DATA[3:0]
DATA[7:0]
DATA[0]
Module 2 of 4
Parity Bus
Parity[1:0]
Parity[3:0]
Parity[0]
N/A
N/A
N/A
23