XC2V8000-5BF957C Xilinx, Inc., XC2V8000-5BF957C Datasheet - Page 63

• Manufacturer Part Number: XC2V8000-5BF957C
• Description: Virtex-II 1.5V Field-Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Table 19: Standard Capacitive Loads
DS031-3 (v1.9) October 12, 2001
Advance Product Specification
Notes:
1.
2.
3.
LVTTL Fast Slew Rate, 2mA drive
LVTTL Fast Slew Rate, 4mA drive
LVTTL Fast Slew Rate, 6mA drive
LVTTL Fast Slew Rate, 8mA drive
LVTTL Fast Slew Rate, 12mA drive
LVTTL Fast Slew Rate, 16mA drive
LVTTL Fast Slew Rate, 24mA drive
LVTTL Slow Slew Rate, 2mA drive
LVTTL Slow Slew Rate, 4mA drive
LVTTL Slow Slew Rate, 6mA drive
LVTTL Slow Slew Rate, 8mA drive
LVTTL Slow Slew Rate, 12mA drive
LVTTL Slow Slew Rate, 16mA drive
LVTTL Slow Slew Rate, 24mA drive
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI 33MHZ 3.3 V
PCI 66 MHz 3.3 V
PCI– X 133 MHz 3.3 V
GTL
GTLP
HSTL Class I
HSTL Class II
HSTL Class III
HSTL Class IV
SSTL2 Class I
SSTL2 Class II
SSTL3 Class I
SSTL3 Class II
AGP
I/O parameter measurements are made with the capacitance values shown above.
I/O standard measurements are reflected in the IBIS model information except where the IBIS format precludes it.
Use of IBIS models results in a more accurate prediction of the propagation delay:
a.
b.
c.
d.
e.
Model the output in an IBIS simulation into the standard capacitive load.
Record the relative time to the V
Remove the capacitance, and model the actual PCB traces (transmission lines) and actual loads from the appropriate IBIS
models for driven devices.
Record the results from the new simulation.
Compare with the capacitance simulation. The increase or decrease in delay from the capacitive load delay simulation should
be added or subtracted from the value above to predict the actual delay.
R
OH
or V
Standard
OL
transition of interest.
www.xilinx.com
1-800-255-7778
Virtex-II 1.5V Field-Programmable Gate Arrays
Csl (pF)
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
10
10
10
20
20
20
20
30
30
30
30
10
0
0
Module 3 of 4
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