XC2V8000-5BF957C Xilinx, Inc., XC2V8000-5BF957C Datasheet - Page 46

• Manufacturer Part Number: XC2V8000-5BF957C
• Description: Virtex-II 1.5V Field-Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Bitstream Encryption
Virtex-II devices have an on-chip decryptor using one or two
sets of three keys for triple-key Data Encryption Standard
(DES) operation. Xilinx software tools offer an optional
encryption of the configuration data (bitstream) with a tri-
ple-key DES determined by the designer.
The keys are stored in the FPGA by JTAG instruction and
retained by a battery connected to the V
device is not powered. Virtex-II devices can be configured
with the corresponding encrypted bitstream, using any of
the configuration modes described previously.
A detailed description of how to use bitstream encryption is
provided in the Virtex-II User Guide. Your local FAE can also
provide specific information on this feature.
Revision History
This section records the change history for this module of the data sheet.
Virtex-II Data Sheet
The Virtex-II Data Sheet contains the following modules:
•
•
DS031-2 (v1.8) October 12, 2001
Advance Product Specification
11/07/00
12/06/00
01/15/01
01/25/01
04/02/01
07/30/01
10/02/01
10/12/01
DS031-1, Virtex-II 1.5V FPGAs:
Ordering Information (Module 1)
DS031-2, Virtex-II 1.5V FPGAs: Functional Description
(Module 2)
Date
R
Version
1.0
1.1
1.2
1.3
1.5
1.6
1.7
1.8
•
•
•
•
•
•
•
Early access draft.
Initial release.
Added values to the tables in the
Switching Characteristics
The data sheet was divided into four modules (per the current style standard). A note was
added to
Under
pull-down resistors was changed to 10 - 60 K
Skipped v1.4 to sync up modules. Reverted to traditional double-column format.
Added
Changed definition of multiply and divide integer ranges under
(DCM).
Made numerous minor edits throughout this module.
Updated descriptions under
Multiplexer
Made clarifying edits under
Introduction and
BATT
Table
Input/Output Individual
Table 6
pin, when the
1.
Buffers,
.
www.xilinx.com
1-800-255-7778
Digital Clock Manager
sections.
Digital Clock Manager
Digitally Controlled Impedance
Partial Reconfiguration
Partial reconfiguration of Virtex-II devices can be accom-
plished in either Slave SelectMAP mode or Boundary-Scan
mode. Instead of resetting the chip and doing a full configu-
ration, new data is loaded into a specified area of the chip,
while the rest of the chip remains in operation. Data is
loaded on a column basis, with the smallest load unit being
a configuration “frame” of the bitstream (device size depen-
dent).
Partial reconfiguration is useful for applications that require
different designs to be loaded into the same area of a chip,
or that require the ability to change portions of a design
without having to reset or reconfigure the entire chip.
•
•
Virtex-II Performance Characteristics
Options, the range of values for optional pull-up and
DS031-3, Virtex-II 1.5V FPGAs:
Characteristics (Module 3)
DS031-4, Virtex-II 1.5V FPGAs:
(Module 4)
Revision
Virtex-II 1.5V Field-Programmable Gate Arrays
W
(DCM), and
from 50 - 100 K
(DCM).
Creating a
(DCI),
Digital Clock Manager
W.
DC and Switching
Pinout Tables
Global Clock
Design.
and
Virtex-II
Module 2 of 4
39