XC2V8000-5BF957C Xilinx, Inc., XC2V8000-5BF957C Datasheet - Page 22

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XC2V8000-5BF957C

Manufacturer Part Number
XC2V8000-5BF957C
Description
Virtex-II 1.5V Field-Programmable Gate Array
Manufacturer
Xilinx, Inc.
Datasheet
Figure
ple configurations.
DS031-2 (v1.8) October 12, 2001
Advance Product Specification
WCLK
A[3:0]
A[4]
WE
WCLK
D
Figure 17: Distributed SelectRAM (RAM16x1S)
A[3:0]
Figure 18: Single-Port Distributed SelectRAM
WE
17,
(BX)
(BY)
(SR)
D
Figure
4
(SR)
(BY)
R
4
4
4
RAM 16x1S
WE
CK
A[4:1]
WG[4:1]
WSG
18, and
WS
RAM 32x1S
RAM
WE0
WE
CK
G[4:1]
WG[4:1]
F[4:1]
WF[4:1]
WSF
WS
WS
WSG
RAM
(RAM32x1S)
RAM
DI
Figure 19
D
DI
DI
D
D
F5MUX
(optional)
illustrate various exam-
D
Q
(optional)
D Q
DS031_02_100900
Output
Registered
Output
DS031_03_110100
Registered
Output
Output
www.xilinx.com
1-800-255-7778
Similar to the RAM configuration, each function generator
(LUT) can implement a 16 x 1-bit ROM. Five configurations
are
ROM128x1, and ROM256x1. The ROM elements are cas-
cadable to implement wider or/and deeper ROM. ROM con-
tents are loaded at configuration.
number of LUTs occupied by each configuration.
Table 10: ROM Configuration
DPRA[3:0]
Figure 19: Dual-Port Distributed SelectRAM
available:
WCLK
A[3:0]
A[3:0]
Virtex-II 1.5V Field-Programmable Gate Arrays
WE
128 x 1
256 x 1
D
16 x 1
32 x 1
64 x 1
ROM
(SR)
(BY)
4
ROM16x1,
4
4
(RAM16x1D)
RAM 16x1D
WE
CK
WE
CK
G[4:1]
WG[4:1]
WSG
G[4:1]
WG[4:1]
WSG
WS
WS
dual_port
RAM
dual_port
RAM
ROM32x1,
DI
DI
Number of LUTs
D
D
Table 10
16 (2 CLBs)
8 (1 CLB)
DS031_04_110100
1
2
4
Module 2 of 4
shows the
ROM64x1,
SPO
DPO
15

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