XC2V8000-5BF957C Xilinx, Inc., XC2V8000-5BF957C Datasheet - Page 10

• Manufacturer Part Number: XC2V8000-5BF957C
• Description: Virtex-II 1.5V Field-Programmable Gate Array
• Manufacturer: Xilinx, Inc.

This DDR mechanism can be used to mirror a copy of the
clock on the output. This is useful for propagating a clock
along the data that has an identical delay. It is also useful for
multiple clock generation, where there is a unique clock
driver for every clock load. Virtex-II devices can produce
many copies of a clock with very little skew.
Each group of two registers has a clock enable signal (ICE
for the input registers, OCE for the output registers, and
TCE for the 3-state registers). The clock enable signals are
active High by default. If left unconnected, the clock enable
for that storage element defaults to the active state.
Each IOB block has common synchronous or asynchronous
set and reset (SR and REV signals).
SR forces the storage element into the state specified by the
SRHIGH or SRLOW attribute. SRHIGH forces a logic “1”.
SRLOW forces a logic “0”. When SR is used, a second input
(REV) forces the storage element into the opposite state. The
reset condition predominates over the set condition. The ini-
tial state after configuration or global initialization state is
defined by a separate INIT0 and INIT1 attribute. By default,
DS031-2 (v1.8) October 12, 2001
Advance Product Specification
CLOCK
R
D1
D2
CLK1
CLK2
(50/50 duty cycle clock)
Q1
Q2
Figure 3: Double Data Rate Registers
DDR MUX
FDDR
www.xilinx.com
1-800-255-7778
Q
the SRLOW attribute forces INIT0, and the SRHIGH attribute
forces INIT1.
For each storage element, the SRHIGH, SRLOW, INIT0,
and INIT1 attributes are independent. Synchronous or
asynchronous set / reset is consistent in an IOB block.
All the control signals have independent polarity. Any
inverter placed on a control input is automatically absorbed.
Each register or latch (independent of all other registers or
latches) (see
•
•
•
•
•
•
•
The synchronous reset overrides a set, and an asynchro-
nous clear overrides a preset.
180° 0°
No set or reset
Synchronous set
Synchronous reset
Synchronous set and reset
Asynchronous set (preset)
Asynchronous reset (clear)
Asynchronous set and reset (preset and clear)
DCM
Virtex-II 1.5V Field-Programmable Gate Arrays
Figure
D1
D2
CLK1
CLK2
4) can be configured as follows:
Q1
Q2
DDR MUX
FDDR
DS031_26_100900
Q
Module 2 of 4
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