XC2V8000-5BF957C Xilinx, Inc., XC2V8000-5BF957C Datasheet - Page 73

• Manufacturer Part Number: XC2V8000-5BF957C
• Description: Virtex-II 1.5V Field-Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Input Clock Tolerances
Table 33: Input Clock Tolerances
DS031-3 (v1.9) October 12, 2001
Advance Product Specification
Notes:
1.
2.
Input Clock Low/high Pulse Width
PSCLK
CLKIN
Input Clock Cycle-Cycle Jitter (Low Frequency Mode)
CLKIN (using DLL outputs
CLKIN (using CLKFX outputs)
Input Clock Cycle-Cycle Jitter (High Frequency Mode)
CLKIN (using DLL outputs
CLKIN (using CLKFX outputs)
Input Clock Period Jitter (Low Frequency Mode)
CLKIN (using DLL outputs
CLKIN (using CLKFX outputs)
Input Clock Period Jitter (High Frequency Mode)
CLKIN (using DLL outputs
CLKIN (using CLKFX outputs)
Feedback Clock Path Delay Variation
CLKFB off-chip feedback
“”DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
Specification also applies to PSCLK.
2
Description
R
1
1
1
1
)
)
)
)
PSCLK_PULSE
CLKIN_PULSE
CLKIN_CYC_JITT_DLL_HF
CLKIN_CYC_JITT_DLL_LF
CLKIN_PER_JITT_DLL_HF
CLKIN_PER_JITT_DLL_LF
CLKFB_DELAY_VAR_EXT
CLKIN_CYC_JITT_FX_HF
CLKIN_PER_JITT_FX_HF
CLKIN_CYC_JITT_FX_LF
CLKIN_PER_JITT_FX_LF
Symbol
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< 1MHz
1 – 10 MHz
10 – 25 MHz
25 – 50 MHz
50 – 100 MHz
100 – 150 MHz
150 – 200 MHz
200 – 250 MHz
250 – 300 MHz
300 – 350 MHz
350 – 400 MHz
> 400 MHz
Constraints
F
CLKIN
Virtex-II 1.5V Field-Programmable Gate Arrays
25.0
25.0
10.0
Min
5.0
3.0
2.4
2.0
1.8
1.5
1.3
1.2
1.1
– 6
±300
±300
±150
±150
Max
±1
±1
±1
±1
±1
Speed Grade
25.0
25.0
10.0
Min
5.0
3.0
2.4
2.0
1.8
1.5
1.3
1.2
1.1
– 5
±300
±300
±150
±150
Max
±1
±1
±1
±1
±1
25.0
25.0
10.0
Min
5.0
3.0
2.4
2.0
1.8
1.5
1.3
1.2
1.1
– 4
±300
±300
±150
±150
Max
±1
±1
±1
±1
±1
Module 3 of 4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ns
ns
ns
ns
ns
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