XC2V8000-5BF957C Xilinx, Inc., XC2V8000-5BF957C Datasheet - Page 70

• Manufacturer Part Number: XC2V8000-5BF957C
• Description: Virtex-II 1.5V Field-Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Virtex-II 1.5V Field-Programmable Gate Arrays
Virtex-II Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted
Global Clock Set-Up and Hold for LVTTL Standard, With DCM
Table 30: Global Clock Set-Up and Hold for LVTTL Standard, With DCM
Module 3 of 4
24
Notes:
1.
2.
3.
Input Setup and Hold Time
Relative to Global Clock Input
Signal for LVTTL Standard.
For data input with different
standards, adjust the setup time
delay by the values shown in
IOB Input Switching
Characteristics Standard
Adjustments, page
No Delay
Global Clock and IFF with DCM
IFF = Input Flip-Flop or Latch
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
DCM output jitter is already included in the timing calculation.
Description
10.
T
PSDCM
Symbol
/T
PHDCM
www.xilinx.com
1-800-255-7778
Device
2v1000
2v1500
2v2000
2v3000
2v4000
2v6000
2v8000
2v250
2v500
2v40
2v80
2.0/– 0.45
2.0/– 0.45
2.0/– 0.45
2.0/– 0.45
2.0/– 0.45
2.0/– 0.45
2.1/– 0.45
2.1/– 0.45
2.1/– 0.45
2.1/– 0.45
TBD
–
6
Speed Grade
2.0/– 0.45
2.0/– 0.45
2.0/– 0.45
2.0/– 0.45
2.0/– 0.45
2.0/– 0.45
2.1/– 0.45
2.1/– 0.45
2.1/– 0.45
2.1/– 0.45
2.1/– 0.45
DS031-3 (v1.9) October 12, 2001
Advance Product Specification
–
5
2.3/– 0.25
2.3/– 0.25
2.3/– 0.25
2.3/– 0.25
2.3/– 0.25
2.3/– 0.25
2.5/– 0.25
2.5/– 0.25
2.5/– 0.25
2.5/– 0.25
2.5/– 0.25
–
4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R