XC2V8000-5BF957C Xilinx, Inc., XC2V8000-5BF957C Datasheet - Page 71
![no-image](/images/no-image-200.jpg)
XC2V8000-5BF957C
Manufacturer Part Number
XC2V8000-5BF957C
Description
Virtex-II 1.5V Field-Programmable Gate Array
Manufacturer
Xilinx, Inc.
Datasheet
1.XC2V8000-5BF957C.pdf
(301 pages)
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Global Clock Set-Up and Hold for LVTTL Standard, Without DCM
,
Table 31: Global Clock Set-Up and Hold for LVTTL Standard, Without DCM
DS031-3 (v1.9) October 12, 2001
Advance Product Specification
Notes:
1.
2.
Input Setup and Hold Time
Relative to Global Clock Input
Signal for LVTTL Standard.
For data input with different
standards, adjust the setup time
delay by the values shown in
Input Switching Characteristics
Standard Adjustments,
page
Full Delay
Global Clock and IFF without
DCM
IFF = Input Flip-Flop or Latch
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
10.
Description
R
IOB
T
PSFD
Symbol
/T
PHFD
www.xilinx.com
1-800-255-7778
Device
2v1000
2v1500
2v2000
2v3000
2v4000
2v6000
2v8000
2v250
2v500
2v40
2v80
Virtex-II 1.5V Field-Programmable Gate Arrays
2.0/0.46
2.0/0.0
2.0/0.0
2.0/0.0
2.0/0.0
2.0/0.0
2.0/0.0
2.0/0.0
2.0/0.0
2.0/0.0
TBD
–
6
Speed Grade
2.0/0.50
2.0/0.50
2.0/0.0
2.0/0.0
2.0/0.0
2.0/0.0
2.0/0.0
2.0/0.0
2.0/0.0
2.0/0.0
2.0/0.0
–
5
2.3/0.50
2.3/0.50
2.3/0.0
2.3/0.0
2.3/0.0
2.3/0.0
2.3/0.0
2.3/0.0
2.3/0.0
2.3/0.0
2.3/0.0
–
4
Module 3 of 4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
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