XC2V8000-5BF957C Xilinx, Inc., XC2V8000-5BF957C Datasheet - Page 28

• Manufacturer Part Number: XC2V8000-5BF957C
• Description: Virtex-II 1.5V Field-Programmable Gate Array
• Manufacturer: Xilinx, Inc.

CLB/Slice Configurations
Table 12
implemented in one of the configurations listed.
Table 12: Logic Resources in One CLB
Table 13: Virtex-II Logic Resources Available in All CLBs
18-Kbit Block SelectRAM Resources
Introduction
Virtex-II devices incorporate large amounts of 18-Kbit block
SelectRAM. These complement the distributed SelectRAM
resources that provide shallow RAM structures imple-
mented in CLBs. Each Virtex-II block SelectRAM is an
18-Kbit true dual-port RAM with two independently clocked
and independently controlled synchronous ports that
access a common storage area. Both ports are functionally
identical. CLK, EN, WE, and SSR polarities are defined
through configuration.
Each port has the following types of inputs: Clock and Clock
Enable, Write Enable, Set/Reset, and Address, as well as
separate Data/parity data inputs (for write) and Data/parity
data outputs (for read).
Operation is synchronous; the block SelectRAM behaves
like a register. Control, address and data inputs must (and
DS031-2 (v1.8) October 12, 2001
Advance Product Specification
Notes:
1.
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
Slices
XC2V250
XC2V500
XC2V40
XC2V80
Device
The carry-chains and SOP chains can be split or cascaded.
4
summarizes the logic resources in one CLB. All of the CLBs are identical and each CLB or slice can be
R
LUTs
CLB Array:
8
112 x 104
Column
24 x 16
32 x 24
40 x 32
48 x 40
56 x 48
64 x 56
80 x 72
96 x 88
Row x
16 x 8
8 x 8
Flip-Flops
8
Number
10,752
14,336
23,040
33,792
46,592
Slices
1,536
3,072
5,120
7,680
256
512
of
MULT_ANDs
Number
10,240
15,360
21,504
28,672
46,080
67,584
93,184
LUTs
1,024
3,072
6,144
516
of
8
Table 13
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1-800-255-7778
SelectRAM or Shift
Max Distributed
shows the available resources in all CLBs.
Carry-Chains
Register (bits)
Arithmetic &
1,081,344
1,490,944
163,840
245,760
344,064
458,752
737,280
16,384
49,152
98,304
8,192
need only) be valid during the set-up time window prior to a
rising (or falling, a configuration option) clock edge. Data
outputs change as a result of the same clock edge.
Configuration
The Virtex-II block SelectRAM supports various configura-
tions, including single- and dual-port RAM and various
data/address aspect ratios. Supported memory configura-
tions for single- and dual-port modes are shown in
Table 14: Dual- and Single-Port Configurations
2
16K x 1 bit
8K x 2 bits
4K x 4 bits
Virtex-II 1.5V Field-Programmable Gate Arrays
Chains
SOP
2
Flip-Flops
Number
10,240
15,360
21,504
28,672
46,080
67,584
93,184
1,024
3,072
6,144
516
of
Distributed
SelectRAM
128 bits
Carry-Chains
Number
112
144
176
208
16
16
32
48
64
80
96
of
512 x 36 bits
Registers
1K x 18 bits
2K x 9 bits
128 bits
Shift
(1)
Module 2 of 4
Chains
Number
of SOP
Table
112
128
160
192
224
TBUF
16
32
48
64
80
96
2
(1)
14.
21