XC2V8000-5BF957C Xilinx, Inc., XC2V8000-5BF957C Datasheet - Page 67
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XC2V8000-5BF957C
Manufacturer Part Number
XC2V8000-5BF957C
Description
Virtex-II 1.5V Field-Programmable Gate Array
Manufacturer
Xilinx, Inc.
Datasheet
1.XC2V8000-5BF957C.pdf
(301 pages)
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Block SelectRAM Switching Characteristics
Table 25: Block SelectRAM Switching Characteristics
TBUF Switching Characteristics
Table 26: TBUF Switching Characteristics
JTAG Test Access Port Switching Characteristics
Table 27: JTAG Test Access Port Switching Characteristics
DS031-3 (v1.9) October 12, 2001
Advance Product Specification
Sequential Delays
Clock CLK to DOUT output
Setup and Hold Times Before Clock CLK
ADDR inputs
DIN inputs
EN input
RST input
WEN input
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
Combinatorial Delays
IN input to OUT output
TRI input to OUT output high-impedance
TRI input to valid data on OUT output
TMS and TDI Setup times before TCK
TMS and TDI Hold times after TCK
Output delay from clock TCK to output TDO
Maximum TCK clock frequency
R
Description
Description
Description
T
T
T
T
T
BWCK
BDCK
BRCK
BACK
BECK
Symbol
T
T
T
www.xilinx.com
1-800-255-7778
BPWH
BCKO
BPWL
/T
/T
/T
/T
/T
BCKA
BCKD
BCKE
BCKR
BCKW
1.0/– 0.46
0.6/– 0.19
0.29/0.0
0.29/0.0
1.4/– 0.7
Symbol
T
2.1
1.2
1.2
–
T
T
OFF
6
ON
Virtex-II 1.5V Field-Programmable Gate Arrays
T
IO
Symbol
T
T
TCKTDO
TCKTAP
F
TAPTK
TCK
Speed Grade
1.1/– 0.50
0.7/– 0.21
0.32/0.0
0.32/0.0
1.5/– 0.7
0.23
0.44
0.44
–
2.4
1.3
1.3
–
6
5
Speed Grade
0.25
0.48
0.48
10.0
–
5.5
0.0
33
5
0.8/– 0.25
0.36/0.0
0.36/0.0
1.2/– 0.5
1.7/– 0.9
2.7
1.5
1.5
–
0.29
0.55
0.55
4
–
4
MHz, max
ns, max
ns, min
ns, min
Units
Module 3 of 4
ns, max
ns, max
ns, max
ns, max
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
Units
Units
21
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