XC2V8000-5BF957C Xilinx, Inc., XC2V8000-5BF957C Datasheet - Page 75

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XC2V8000-5BF957C

Manufacturer Part Number
XC2V8000-5BF957C
Description
Virtex-II 1.5V Field-Programmable Gate Array
Manufacturer
Xilinx, Inc.
Datasheet
Miscellaneous Timing Parameters
Table 36: Miscellaneous Timing Parameters
Frequency Synthesis
Table 37: Frequency Synthesis
Parameter Cross Reference
Table 38: Parameter Cross Reference
DS031-3 (v1.9) October 12, 2001
Advance Product Specification
Notes:
1.
2.
Time Required to Achieve LOCK
Using DLL outputs
Using CLKFX outputs
Additional lock time with
fine-phase shifting
Fine-Phase Shifting
Absolute shifting range
Delay Lines
Tap delay resolution
DLL_CLKOUT_{MIN|MAX}_LF
DFS_CLKOUT_{MIN|MAX}_LF
DLL_CLKIN_{MIN|MAX}_LF
DFS_CLKIN_{MIN|MAX}_LF
DLL_CLKOUT_{MIN|MAX}_HF
DFS_CLKOUT_{MIN|MAX}_HF
DLL_CLKIN_{MIN|MAX}_HF
DFS_CLKIN_{MIN|MAX}_HF
“”DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
Specification also applies to PSCLK.
Description
R
(1)
Libraries Guide
CLKFX_MULTIPLY
CLKFX_DIVIDE
Attribute
LOCK_DLL_FINE_SHIFT
FINE_SHIFT_RANGE
LOCK_DLL_50_60
LOCK_DLL_40_50
LOCK_DLL_30_40
LOCK_DLL_24_30
DCM_TAP_MAX
LOCK_FX_MAX
DCM_TAP_MIN
LOCK_FX_MIN
LOCK_DLL_60
LOCK_DLL
Symbol
www.xilinx.com
1-800-255-7778
CLKOUT_FREQ_{1X|2X|DV}_LF
CLKOUT_FREQ_FX_LF
CLKIN_FREQ_DLL_LF
CLKIN_FREQ_FX_LF
CLKOUT_FREQ_{1X|DV}_HF
CLKOUT_FREQ_FX_HF
CLKIN_FREQ_DLL_HF
CLKIN_FREQ_FX_HF
Constraints
50 - 60 MHz
40 - 50 MHz
30 - 40 MHz
24 - 30 MHz
> 60MHz
F
CLKIN
Virtex-II 1.5V Field-Programmable Gate Arrays
Min
2
1
120.0
20.0
25.0
50.0
90.0
10.0
10.0
50.0
10.0
30.0
50.0
– 6
Data Sheet
Speed Grade
120.0
20.0
25.0
50.0
90.0
10.0
10.0
50.0
10.0
30.0
50.0
– 5
Max
120.0
20.0
25.0
50.0
90.0
10.0
10.0
50.0
10.0
30.0
50.0
32
32
– 4
Module 3 of 4
Units
ms
ms
m
m
m
m
m
m
ns
ps
ps
s
s
s
s
s
s
29

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