ADSP-TS101S Analog Devices, ADSP-TS101S Datasheet - Page 9

• Manufacturer Part Number: ADSP-TS101S
• Description: Embedded Processor
• Manufacturer: Analog Devices

Clock Domains
As shown in
SCLK (system clock) and LCLK (local clock), that drive its
two major clock domains:
Connecting SCLK and LCLK to the same clock source is a
requirement for the device. Using an integer clock multipli-
cation value provides predictable cycle-by-cycle operation, a
requirement of fault-tolerant systems and some multi-
processing systems.
Noninteger values are completely functional and acceptable for
applications that do not require predictable cycle-by-cycle
operation.
Output Pin Drive Strength Control
Pins CONTROLIMP2-0 and DS2-0 work together to control
the output drive strength of two groups of pins, the
Address/Data/Control pin group and the Link pin group.
CONTROLIMP2-0 independently configures the two pin
groups to the maximum drive strength or to a digitally controlled
drive strength that is selectable by the DS2-0 pins (see
on Page
for a pin group the DS2-0 pins determine one of eight strength
levels for that group (see
strength selected varies the slew rate of the driver. Drive strength
0 (DS2-0 = 000) is the weakest and slowest slew rate. Drive
strength 7 (DS2-0 = 111) is the strongest and fastest slew rate.
CROSSCORE is a trademark of Analog Devices, Inc.
VisualDSP++ is a trademark of Analog Devices, Inc.
REV. A
SCLK (system clock). Provides clock input for the
external bus interface and defines the ac specification
reference for the external bus signals. The external bus
interface runs at 1 the SCLK frequency. A DLL locks
internal SCLK to SCLK input.
LCLK (local clock). Provides clock input to the internal
clock driver, CCLK, which is the internal clock for the
core, internal buses, memory, and link ports. The instruc-
tion execution rate is equal to CCLK. A PLL from LCLK
generates CCLK which is phase-locked. The LCLKRAT
pins define the clock multiplication of LCLK to CCLK
(see
CCLK via a software programmable divisor. RESET
must be asserted until LCLK is stable and within speci-
fication for at least 2 ms. This applies to power-up as well
as any dynamic modification of LCLK after power-up.
Dynamic modification may include LCLK going out of
specification as long as RESET is asserted.
LCLKRATx
SCLK_P
LCLK_P
Table
17). If the digitally controlled drive strength is selected
LCTLx REGISTER
Figure
4). The link port clock is generated from
SPD BITS,
Figure 4. Clock Domains
4, the ADSP-TS101S has two clock inputs,
DLL
DLL
DLL
PLL
Table 14 on Page
DLL
/LR
CCLK
(INSTRUCTION RATE)
LxCLKOUT/LxCLKIN
(LINK PORT RATE)
EXTERNAL INTERFACE
17). The drive
Table 13
–9–
The stronger drive strengths are useful for high frequency
switching while the lower strengths may allow use of a relaxed
design methodology. The strongest drive strengths have a larger
di/dt and thus require more attention to signal integrity issues
such a ringing, reflections and coupling. Also a larger di/dt can
increase external supply rail noise, which impacts power supply
and power distribution design.
The drive strengths for the EMU, CPA, and DPA pins are not
controllable and are fixed to the maximum level.
For drive strength calculation, see
Page
Power Supplies
The ADSP-TS101S has separate power supply connections for
internal logic (V
(V
supplies must meet the 1.2 V requirement. The I/O buffer
(V
The analog supply (V
produce a stable clock, systems must provide a clean power
supply to power input V
to bypassing the V
The required power-on sequence for the DSP is to provide V
(and V
Filtering Reference Voltage and Clocks
Figure 5
LCLK_N. This circuit provides the reference voltage for the
switching voltage, system clock, and local clock references.
Development Tools
The ADSP-TS101S is supported with a complete set of
CROSSCORE™ software and hardware development tools,
including Analog Devices emulators and VisualDSP++™ devel-
opment environment. The same emulator hardware that
supports other TigerSHARC processors also fully emulates the
ADSP-TS101S.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an algebraic
syntax), an archiver (librarian/library builder), a linker, a loader,
a cycle-accurate instruction-level simulator, a C/C++ compiler,
and a C/C++ runtime library that includes DSP and mathemat-
ical functions. A key point for these tools is C/C++ code
DD_IO
DD_IO
31.
R1: 2k
R2: 1.67k
C1: 1 F CAPACITOR (SMD)
C2: 1nF CAPACITOR (HF SMD) PLACED CLOSE TO DSP’S PINS
DD_A
) power supply. The internal (V
) supply must meet the 3.3 V requirement.
V
DD_IO
shows a possible circuit for filtering V
Figure 5. V
) before V
SERIES RESISTOR
SERIES RESISTOR
DD
R1
R2
DD_A
), analog circuits (V
DD_IO
DD_A
REF
supply.
DD_A
, SCLK_N, and LCLK_N Filter
) powers the clock generator PLLs. To
.
C1
. Designs must pay critical attention
V
SS
ADSP-TS101S
C2
Output Drive Currents on
DD_A
DD
) and analog (V
), and I/O buffer
REF
, SCLK_N, and
SCLK_N
LCLK_N
V
REF
DD_A
)
DD