ADSP-TS101S Analog Devices, ADSP-TS101S Datasheet - Page 2

• Manufacturer Part Number: ADSP-TS101S
• Description: Embedded Processor
• Manufacturer: Analog Devices

ADSP-TS101S
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 2
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . 11
STRAP PIN FUNCTION DESCRIPTIONS . . . . . . . 18
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 19
484-BALL PBGA PIN CONFIGURATIONS . . . . . . 36
625-BALL PBGA PIN CONFIGURATIONS . . . . . . 39
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . 42
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . 43
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Dual Compute Blocks . . . . . . . . . . . . . . . . . . . . . . . . 3
Data Alignment Buffer (DAB) . . . . . . . . . . . . . . . . . . 4
Dual Integer ALUs (IALUs) . . . . . . . . . . . . . . . . . . . 4
Program Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . 4
On-Chip SRAM Memory . . . . . . . . . . . . . . . . . . . . . 5
External Port
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Link Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Timer and General-Purpose I/O . . . . . . . . . . . . . . . . 8
Reset and Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . . 8
Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Output Pin Drive Strength Control . . . . . . . . . . . . . . 9
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Filtering Reference Voltage and Clocks . . . . . . . . . . . 9
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Designing an Emulator-Compatible DSP
Additional Information . . . . . . . . . . . . . . . . . . . . . . 11
Pin States at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . 20
ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . 20
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . 21
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . 31
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Environmental Conditions . . . . . . . . . . . . . . . . . . . . 35
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . 4
Flexible Instruction Set . . . . . . . . . . . . . . . . . . . . . 4
Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Multiprocessor Interface . . . . . . . . . . . . . . . . . . . . . 5
SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . 6
EPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . 6
Board (Target) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
General AC Timing . . . . . . . . . . . . . . . . . . . . . . . 21
Link Ports Data Transfer
Output Disable Time . . . . . . . . . . . . . . . . . . . . . . 32
Output Enable Time . . . . . . . . . . . . . . . . . . . . . . 32
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . 33
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . 35
(Off-Chip Memory/Peripherals Interface) . . . . . . 5
and Token Switch Timing . . . . . . . . . . . . . . . . . 28
–2–
GENERAL DESCRIPTION
The ADSP-TS101S TigerSHARC processor is an ultra high per-
formance, static superscalar processor optimized for large signal
processing tasks and communications infrastructure. The DSP
combines very wide memory widths with dual computation
blocks—supporting 32- and 40-bit floating-point and 8-, 16-,
32-, and 64-bit fixed-point processing—to set a new standard of
performance for digital signal processors. The TigerSHARC pro-
cessor’s static superscalar architecture lets the processor execute
up to four instructions each cycle, performing twenty-four 16-bit
fixed-point operations or six floating-point operations.
Three independent 128-bit wide internal data buses, each
connecting to one of the three 2M bit memory banks, enable
quad word data, instruction, and I/O accesses and provide
14.4G bytes per second of internal memory bandwidth.
Operating at 300 MHz, the ADSP-TS101S processor’s core has
a 3.3 ns instruction cycle time. Using its Single-Instruction,
Multiple-Data (SIMD) features, the ADSP-TS101S can
perform 2.4 billion 40-bit MACs or 600 million 80-bit MACs
per second.
benchmarks.
Table 1. General-Purpose Algorithm Benchmarks
at 300 MHz
Table 2. 3G Wireless Algorithm Benchmarks
1
2
3
The ADSP-TS101S is code compatible with the other Tiger-
SHARC processors.
Benchmark
32-bit Algorithm, 600 million MACs/s peak performance
1024 Point Complex FFT (Radix
2)
50-tap FIR on 1024 input
Single FIR MAC
16-bit Algorithm, 2.4 billion MACs/s peak performance
256 Point Complex FFT (Radix 2) 3.67 µs
50-tap FIR on 1024 input
Single FIR MAC
Single Complex FIR MAC
I/O DMA Transfer Rate
External port
Link ports (each)
Benchmark
Turbo Decode
Viterbi Decode
Complex Correlation
The Execution Speed is in Instruction Cycles Per Second.
Adaptive Multi Rate (AMR)
Megachips per second (Mcps)
3.84 Mcps
384 kbps Data Channel
12.2 kbps AMR
Table 1
3
with a Spreading Factor of 256
and
2
Voice Channel
Table 2
show the DSP’s performance
Speed
32.78 µs
91.67 µs
1.83 ns
24.0 µs
0.47 ns
1.9 ns
800M bytes/s n/a
250M bytes/s n/a
Execution
(MIPS)
51 MIPS
0.86 MIPS
0.27 MIPS
REV. A
Clock
Cycles
9,835
27,500
0.55
1,100
7,200
0.14
0.57
1