ADSP-TS101S Analog Devices, ADSP-TS101S Datasheet - Page 8

• Manufacturer Part Number: ADSP-TS101S
• Description: Embedded Processor
• Manufacturer: Analog Devices

ADSP-TS101S
The DMA controller also supports two-dimensional transfers.
The DMA controller can access and transfer two-dimensional
memory arrays on any DMA transmit or receive channel. These
transfers are implemented with index, count, and modify
registers for both the X and Y dimensions.
The DMA controller performs the following DMA operations:
Link Ports
The DSP’s four link ports provide additional 8-bit bidirectional
I/O capability. With the ability to operate at a double data rate—
latching data on both the rising and falling edges of the clock—
running at 125 MHz, each link port can support up to
250M bytes per second, for a combined maximum throughput
of 1G bytes per second.
The link ports provide an optional communications channel that
is useful in multiprocessor systems for implementing point to
point interprocessor communications. Applications can also use
the link ports for booting.
Each link port has its own double-buffered input and output
registers. The DSP’s core can write directly to a link port’s
transmit register and read from a receive register, or the DMA
controller can perform DMA transfers through eight (four
transmit and four receive) dedicated link port DMA channels.
Each link port has three signals that control its operation.
LxCLKOUT and LxCLKIN implement clock/acknowledge
handshaking. LxDIR indicates the direction of transfer and is
used only when buffering the LxDAT signals. An example appli-
cation would be using differential low-swing buffers for long
twisted-pair wires. LxDAT provides the 8-bit data bus
input/output.
Applications can program separate error detection mechanisms
for transmit and receive operations (applications can use the
checksum mechanism to implement consecutive link port trans-
fers), the size of data packets, and the speed at which bytes are
transmitted.
External port block transfers. Four dedicated bidirec-
tional DMA channels transfer blocks of data between the
DSP’s internal memory and any external memory or
memory-mapped peripheral on the external bus. These
transfers support master mode and handshake mode
protocols.
Link port transfers. Eight dedicated DMA channels (four
transmit and four receive) transfer quad word data only
between link ports and between a link port and internal
or external memory. These transfers only use handshake
mode protocol. DMA priority rotates between the four
receive channels.
AutoDMA transfers. Two dedicated unidirectional DMA
channels transfer data received from an external bus
master to internal memory or to link port I/O. These
transfers only use slave mode protocol, and an external
bus master must initiate the transfer.
–8–
Under certain conditions, the link port receiver can initiate a
token switch to reverse the direction of transfer; the transmitter
becomes the receiver and vice versa.
Timer and General-Purpose I/O
The ADSP-TS101S has a timer pin (TMR0E) that generates
output when a programmed timer counter has expired. Also, the
DSP has four programmable general-purpose I/O pins
(FLAG3–0) that can function as either single bit input or output.
As outputs, these pins can signal peripheral devices; as inputs,
they can provide the test for conditional branching.
Reset and Booting
The ADSP-TS101S has two levels of reset (see reset specifica-
tions
The DSP can be reset internally (core reset) by setting the
SWRST bit in SQCTL. The core is reset, but not the external
port or I/O.
After reset, the ADSP-TS101S has four boot options for
beginning operation:
The ADSP-TS101S core always exits from reset in the idle state
and waits for an interrupt. Some of the interrupts in the interrupt
vector table are initialized and enabled after reset.
Low Power Operation
The ADSP-TS101S can enter a low power sleep mode in which
its core does not execute instructions, reducing power consump-
tion to a minimum. The ADSP-TS101S exits sleep mode when
it senses a falling edge on any of its IRQ3–0 interrupt inputs. The
interrupt, if enabled, causes the ADSP-TS101S to execute the
corresponding interrupt service routine. This feature is useful for
systems that require a low power standby mode.
Power-up reset—After power-up of the system, and strap
options are stable, the RESET pin must be asserted (low).
Normal reset—For any resets following the power-up
reset sequence, the RESET pin must be asserted.
Boot from EPROM. The DSP defaults to EPROM
booting when the BMS pin strap option is set low. See
STRAP PIN FUNCTION DESCRIPTIONS on
Page
Boot by an external master (host or another ADSP-
TS101S). Any master on the cluster bus can boot the
ADSP-TS101S through writes to its internal memory or
through auto DMA.
Boot by link port. All four receive link DMA channels are
initialized after reset to transfer a 256-word block to
internal memory address 0 to 255, and to issue an
interrupt at the end of the block (similar to EP DMA).
The corresponding DMA interrupts are set to address
zero (0).
No boot—Start running from an external memory. Using
the ‘no boot’ option, the ADSP-TS101S must start
running from an external memory, caused by asserting
one of the IRQ3–0 interrupt signals.
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