ADSP-TS101S Analog Devices, ADSP-TS101S Datasheet - Page 13

• Manufacturer Part Number: ADSP-TS101S
• Description: Embedded Processor
• Manufacturer: Analog Devices

Table 5. Pin Definitions—External Port Bus Controls (continued)
1
2
3
4
Table 6. Pin Definitions—External Port Arbitration
REV. A
Signal
MS1–0
MSH
BRST
Type column symbols: A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;
pd = Internal pull-down approximately 100 k ; pu = Internal pull-up approximately 100 k ; T = Three-state
Term (for termination) column symbols: epd = External pull-down approximately 10 k to V
nc = Not connected; au = Always used.
The address and data buses may float for several cycles during bus mastership transitions between a TigerSHARC processor and a host. Floating in this
The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
See
The internal pull-down may not be sufficient. A stronger pull-down may be necessary.
Signal
BR7–0
ID2–0
BM
BOFF
BUSLOCK
HBR
Type column symbols: A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;
pd = Internal pull-down approximately 100 k ; pu = Internal pull-up approximately 100 k ; T = Three-state
Term (for termination) column symbols: epd = External pull-down approximately 10 k to V
nc = Not connected; au = Always used.
case means that these inputs are not driven by any source and that dc-biased terminations are not present. It is not necessary to add pull-ups as there are
no reliability issues and the worst-case power consumption for these floating inputs is negligible. Unconnected address pins may require pull-ups or pull-
downs to avoid erroneous slave accesses, depending on the system. Unconnected data pins may be left floating.
ELECTRICAL CHARACTERISTICS on Page 19
1
2
2
1
2
3
Type
O/T (pu
O/T (pu
I/O/T
(pu
Type
I/O
I (pd
O (pd
I
O/T (pu
I
3
)
2
)
2
)
3
3
2
)
)
)
Term
nc
nc
nc
Term
epu
au
au
epu
nc
epu
Description
Memory Select. MS0 or MS1 is asserted whenever the DSP accesses memory
banks 0 or 1, respectively. MS1–0 are decoded memory address pins that
change concurrently with ADDR pins. When ADDR31:26 = 0b000010, MS0
is asserted. When ADDR31:26 = 0b000011, MS1 is asserted. In multipro-
cessor systems, the master DSP drives MS1–0.
Memory Select Host. MSH is asserted whenever the DSP accesses the host
address space (ADDR31:28
pin that changes concurrently with ADDR pins. In a multiprocessor system,
the bus master DSP drives MSH.
Burst. The current bus master (DSP or host) asserts this pin to indicate that
it is reading or writing data associated with consecutive addresses. A slave
device can ignore addresses after the first one and increment an internal
address counter after each transfer. For host-to-DSP burst accesses, the DSP
increments the address automatically while BRST is asserted.
Description
Multiprocessing Bus Request Pins. Used by the DSPs in a multiprocessor
system to arbitrate for bus mastership. Each DSP drives its own BRx line
(corresponding to the value of its ID2–0 inputs) and monitors all others. In
systems with fewer than eight DSPs, set the unused BRx pins high.
Multiprocessor ID. Indicates the DSP’s ID. From the ID, the DSP determines
its order in a multiprocessor system. These pins also indicate to the DSP which
bus request (BR0–BR7) to assert when requesting the bus: 000 = BR0,
001 = BR1, 010 = BR2, 011 = BR3, 100 = BR4, 101 = BR5, 110 = BR6, or
111 = BR7. ID2–0 must have a constant value during system operation and
can change during reset only.
Bus Master. The current bus master DSP asserts BM. For debugging only. At
reset this is a strap pin. For more information, see
Back Off. A deadlock situation can occur when the host and a DSP try to read
from each other’s bus at the same time. When deadlock occurs, the host can
assert BOFF to force the DSP to relinquish the bus before completing its
outstanding transaction, but only if the outstanding transaction is to host
memory space (MSH).
Bus Lock Indication. Provides an indication that the current bus master has
locked the bus.
Host Bus Request. A host must assert HBR to request control of the DSP’s
external bus. When HBR is asserted in a multiprocessing system, the bus
master relinquishes the bus and asserts HBG once the outstanding transaction
is finished.
for maximum and minimum current consumption for pull-up and pull-down resistances.
–13–
SS
SS
; epu = External pull-up approximately 10 k to V
; epu = External pull-up approximately 10 k to V
0b0000). MSH is a decoded memory address
Table 16 on Page
ADSP-TS101S
DD-IO
DD-IO
18.