ADSP-TS101S Analog Devices, ADSP-TS101S Datasheet - Page 29

• Manufacturer Part Number: ADSP-TS101S
• Description: Embedded Processor
• Manufacturer: Analog Devices

Table 25. Link Ports—Receive
1
2
3
REV. A
Parameter
Timing Requirements
t
t
t
t
t
t
t
Switching Characteristics
t
t
The link clock ratio (LR) is 2, 3, 4, or 8 as set by the SPD bits in the LCTLx register.
The formula for this parameter applies when LR is 2.
The formula for this parameter applies when LR is 3, 4, or 8.
L
L
L
L
L
DIS
DIH
CONNV
CONNOW
X
X
X
X
X
CLK_R
CLKH_R
CLKH_R
CLKL_R
CLKL_R
X
1
X
X
X
X
2
3
2
3
LxCLKOUT
LxDAT7–0
LxCLKIN
Receive Link Clock Period
Receive Link Clock Width High
Receive Link Clock Width High
Receive Link Clock Width Low
Receive Link Clock Width Low
LxDAT7–0 Input Setup
LxDAT7–0 Input Hold
Connectivity Pulse Valid
Connectivity Pulse Output Width
LxDIR
t
CONNV
0
1
2
t
LxCLK_Rx
t
CONNOW
Figure 11. Link Ports—Receive
3
4
t
t
LxCLKH_Rx
LxCLKL_Rx
5
–29–
6
t
DIS
7
t
DIH
8
Min
0.9 LR 4 ns or
0.9 LR + t
whichever is larger
0.33 t
0.4 t
0.33 t
0.4 t
0.6
0.6
0
1.5 t
9
t
DIS
L
L
L
X
X
X
L
L
CLK_R
CLK_R
CLK_R
10
X
X
CLK_R
CLK_R
t
CCLK
DIH
11
X
X
X
X
X
,
12
13
Max
1.1 LR t
0.66 t
0.6 t
0.66 t
0.6 t
2.5 t
14
ADSP-TS101S
15
L
L
L
X
X
X
L
L
CLK_R
CLK_R
CLK_R
X
X
CLK_R
CLK_R
CCLK
X
X
X
X
X
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns