ADSP-TS101S Analog Devices, ADSP-TS101S Datasheet - Page 6

• Manufacturer Part Number: ADSP-TS101S
• Description: Embedded Processor
• Manufacturer: Analog Devices

ADSP-TS101S
SDRAM Controller
The SDRAM controller controls the ADSP-TS101S processor’s
transfers of data to and from synchronous DRAM (SDRAM).
The throughput is 32 or 64 bits per SCLK cycle using the external
port and SDRAM control pins.
The SDRAM interface provides a glueless interface with
standard SDRAMs—16M bit, 64M bit, 128M bit, and
256M bit. The DSP directly supports a maximum of
64M words
mapped in external memory in the DSP’s unified memory map.
EPROM Interface
The ADSP-TS101S can be configured to boot from external
8-bit EPROM at reset through the external port. An automatic
process (which follows reset) loads a program from the EPROM
into internal memory. This process uses 16 wait cycles for each
INTERNAL REGISTERS (UREGS)
INTERNAL MEMORY 0
INTERNAL MEMORY 2
INTERNAL MEMORY 1
INTERNAL SPACE
RESERVED
RESERVED
RESERVED
RESERVED
32 bit of SDRAM. The SDRAM interface is
0x00300000
0x00280000
0x00200000
0x00180000
0x00100000
0x00080000
0x00000000
0x003FFFFF
0x001807FF
0x0010FFFF
0x0008FFFF
0x0000FFFF
Figure 2. Memory Map
–6–
read access. During booting, the BMS pin functions as the
EPROM chip select signal. The EPROM boot procedure uses
DMA channel 0, which packs the bytes into 32-bit instructions.
Applications can also access the EPROM (write flash memories)
during normal operation through DMA.
The EPROM or Flash Memory interface is not mapped in the
DSP’s unified memory map. It is a byte address space limited to
a maximum of 16M bytes (24 address bits). The EPROM or
Flash Memory interface can be used after boot via a DMA.
DMA Controller
The ADSP-TS101S processor’s on-chip DMA controller, with
14 DMA channels, provides zero-overhead data transfers without
processor intervention. The DMA controller operates indepen-
dently and invisibly to the DSP’s core, enabling DMA operations
INTERNAL MEMORY
PROCESSOR ID 7
PROCESSOR ID 6
PROCESSOR ID 5
PROCESSOR ID 4
PROCESSOR ID 3
PROCESSOR ID 2
PROCESSOR ID 1
PROCESSOR ID 0
GLOBAL SPACE
BROADCAST
RESERVED
BANK 1
BANK 0
SDRAM
(MSSD)
(MSH)
HOST
(MS1)
(MS0)
0xFFFFFFFF
0x08000000
0x04000000
0x03800000
0x03400000
0x03000000
0x02800000
0x02400000
0x02000000
0x003FFFFF
0x00000000
0x0C000000
0x03C00000
0x02C00000
0x01C00000
0x10000000
OF INTERNAL SPACE
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